Embedded Capacitor RDL Layout for Low-Inductance IC Packaging
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges in minimizing signal path length and inductance between embedded capacitors and semiconductor dies, which affects the capacitors' ability to store energy during transient power supply events and respond to high-frequency signals.
Innovation Solution
Incorporating a redistribution layer (RDL) on the substrate of an embedded capacitor package to align capacitor terminals with die interconnects, allowing for finer pitch metal interconnects and reducing signal path length, thereby minimizing inductance in the capacitive loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitor terminals are directly connected to die interconnects without RDL, then the structure is simpler, but the pitch mismatch prevents optimal alignment and increases signal path length
Solution Approach 1:
The patent introduces a redistribution layer (RDL) that adds an intermediate metallization dimension between the capacitor terminals and die interconnects. This additional layer allows pitch transformation by redistributing connections in a different spatial plane, enabling alignment between components with mismatched pitch patterns without increasing vertical complexity.
Solution Approach 2:
The RDL acts as an intermediary element that mediates the connection between capacitor terminals and die interconnects. It transforms the pitch pattern from one component to match the other, serving as a buffer layer that resolves the pitch mismatch problem while maintaining electrical connectivity.
2Manufacturing precision
If additional metallization layers (RDL) are added to align pitch, then alignment precision improves, but manufacturing complexity increases
Solution Approach 1:
The interconnect structure is segmented into distinct functional layers: the base substrate metallization, the intermediate RDL layer with pitch-transforming patterns, and the top die attachment layer. This segmentation allows each layer to be optimized independently for its specific function, making the overall complex structure manageable through modular fabrication steps.
3Reliability
If signal path length is reduced by direct connection, then inductance is minimized, but pitch mismatch prevents proper alignment
Solution Approach 1:
The RDL is designed with locally optimized pitch patterns that match the specific geometry of both capacitor terminals and die interconnects. Different regions of the RDL have different pitch characteristics, allowing optimal local alignment while maintaining overall signal path efficiency. This local quality adjustment resolves the pitch mismatch without requiring uniform changes throughout the entire structure.
Data Source
AI summary
Package substrate with embedded capacitor package with a redistribution layer(s) (RDL(s)) for aligning capacitor terminals to die interconnects of a semiconductor die (“die”) in an integrated circuit (IC) package, and related IC packages and fabrication methods. The capacitor package can be embedded in a package substrate of an IC package, such as to provide a decoupling capacitance or filter for a die of the IC package. A RDL(s) is built on a substrate of a capacitor of the capacitor package such that RDL interconnects of the RDL(s) are coupled to capacitor terminals of the capacitor. The RDL(s) redistributes connections to the capacitor terminals of the capacitor, to a desired pattern and/or pitch to align the capacitor terminals with die interconnects of a die coupled to the package substrate of the IC package. This minimizes signal path length between the capacitor and die to minimize inductance in the capacitive loop.