Embedded Capacitor in Semiconductor Chip for Noise Reduction

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Solution Overview

Problem

High-speed operation of semiconductor devices on low voltage generates significant electrical noise, degrading the reliability of semiconductor chips.

Innovation Solution

An embedded capacitor is integrated into the semiconductor chip, comprising a dielectric layer with a high dielectric constant and external connection reinforcing lines that form a capacitor with the power supply and ground pads, reducing noise and improving reliability without additional processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed operation with low operating voltage is implemented, then operating speed is improved, but electrical noise increases and reliability deteriorates

Engineering Contradiction:
Improveoperating speedVSAvoidelectrical reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent merges the capacitor structure with the existing power supply and ground pads by forming the capacitor electrodes directly on these pads. The dielectric layer is formed between the power supply pad and ground pad, effectively combining the power delivery function with noise filtering in a single integrated structure, thereby improving reliability without sacrificing speed

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a dielectric layer as an intermediary between the power supply pad and ground pad to form a capacitor structure. This dielectric layer acts as a mediator that stores electrical energy and filters noise, allowing the system to maintain high-speed operation while improving electrical reliability through the intermediary energy storage element

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional capacitor structures are added to reduce noise, then electrical reliability is improved, but device complexity and manufacturing steps increase

Engineering Contradiction:
Improveelectrical reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the capacitor function with the existing power supply and ground pad structures. By forming the capacitor electrodes directly on these pads and using the dielectric layer between them, the design eliminates the need for separate capacitor components and their associated routing, thereby reducing device complexity while maintaining noise filtering capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The power supply pad and ground pad serve dual functions: they provide power delivery and simultaneously form the electrodes of the capacitor structure. The existing structural elements serve the additional purpose of noise filtering, eliminating the need for dedicated noise reduction components and simplifying the overall device architecture

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The embedded capacitor stabilizes power and ground voltage supply, reducing noise and enhancing the electrical reliability of semiconductor chips and apparatuses.

Implementation Method 1

a dielectric layer formed over the uppermost internal wiring line in such a way as to expose the power supply pad and the ground pad

Methodology Applied
Scientific EffectDielectric: Dielectric

Implementation Method 2

an embedded capacitor constituted by the external connection reinforcing line, and the dielectric layer and a portion of the uppermost internal wiring line which correspond to the external connection reinforcing line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8907451B2Semiconductor chip and semiconductor apparatus with embedded capacitor
Publication Date: 2014.12.09 SK HYNIX INC
  • US8907451B2 patent drawing
  • US8907451B2 patent drawing
  • US8907451B2 patent drawing

AI summary

A semiconductor chip includes a semiconductor substrate having one and the other surfaces and formed with a plurality of semiconductor devices; an internal wiring layer having multi-layered internal wiring lines which are formed over the one surface and are electrically connected with the plurality of semiconductor devices, an uppermost internal wiring line among the internal wiring lines being formed with a power supply pad and a ground pad; a dielectric layer formed over the uppermost internal wiring line in such a way as to expose the power supply pad and the ground pad; an external connection reinforcing line formed over the power supply pad or the ground pad which is exposed, and extending onto the dielectric layer; and an embedded capacitor constituted by the external connection reinforcing line, and the dielectric layer and a portion of the uppermost internal wiring line which correspond to the external connection reinforcing line.