Embedded Capacitor in Semiconductor Package Molding Layer
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Solution Overview
Problem
High-speed operation of semiconductor devices leads to increased power/ground noise, which is not effectively mitigated by current decoupling capacitor methods, causing power supply interruptions and signal interference.
Innovation Solution
Incorporating a capacitor within the semiconductor package's molding layer, connected to the redistribution conductive layers, to stabilize power supply and reduce impedance, thereby shortening the alternating current path and reducing noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are added to power transmission paths to stabilize power/ground supply, then power supply stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the decoupling capacitor with the molding layer structure, integrating the capacitor as an embedded component within the molding material rather than as a separate external component. This combining approach maintains power supply stability while reducing overall package complexity and component count.
Solution Approach 2:
The capacitor is nested within the molding layer, with the capacitor completely embedded inside the molding material. This nesting structure allows the capacitor to be housed within the existing package volume without requiring additional external space or complex interconnection structures.
2Speed
If signal transmission speed and capacity are increased, then data processing capability is improved, but power/ground noise increases
Solution Approach 1:
The decoupling capacitor is positioned in close proximity to the power input terminal and the sub semiconductor chip, creating a short current path that enables the capacitor to respond quickly to power noise before it propagates through the system. This preliminary positioning allows the capacitor to mitigate noise at its source rather than attempting to filter it later in the signal path.
Solution Approach 2:
The patent creates a localized decoupling region near the power input terminal with high capacitance density, concentrating the noise filtering function in the specific area where power/ground noise is most problematic. This local quality approach targets the noise issue at its source without requiring system-wide modifications.
3Object-generated harmful factors
If current decoupling capacitor methods are used, then some power noise is reduced, but noise reduction effectiveness is insufficient for high-speed operation
Solution Approach 1:
The patent transitions from traditional external or surface-mounted capacitor configurations to a three-dimensional embedded structure within the molding layer. This dimensional change allows the capacitor to be positioned optimally in 3D space, creating shorter current paths and improving the effectiveness of noise reduction in high-speed operation scenarios.
Solution Approach 2:
The patent modifies the physical parameters of the capacitor configuration, including its position, size, and integration method within the molding layer. By changing these parameters, the capacitor achieves better electrical connection and shorter current paths, significantly improving noise reduction effectiveness for high-speed applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces impedance and noise in the power supply path, ensuring stable power delivery and improved signal transmission even with increased signal transmission speeds and capacities.
Implementation Method 1
a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion between the first electrode and the second electrode
Implementation Method 2
shortening the alternating current path and reducing noise interference
Data Source
AI summary
A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.