Embedded Substrate Capacitor Side-Wall Coupling for Low PDN Impedance
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Solution Overview
Problem
Existing packages with integrated devices and substrates face challenges in achieving optimal electrical performance due to impedance and voltage droop issues, which are not adequately addressed by current coupling methods between capacitors and substrates.
Innovation Solution
The package design incorporates a substrate with dielectric layers, interconnects, and capacitors where the capacitors are embedded partially within the substrate, with solder interconnects coupled to the side surfaces of the terminals and interconnects, reducing impedance and voltage droop by aligning the capacitor's side surfaces with the substrate's metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional non-side wall coupling methods are used to connect capacitors to substrates, then the device complexity is reduced and ease of manufacture is improved, but the impedance and voltage droop performance deteriorate
Solution Approach 1:
The patent transitions from traditional top-down or bottom-up coupling methods to side-wall coupling, utilizing the lateral dimension of the capacitor terminals. The side surfaces of the capacitor terminals are coupled to side walls of substrate interconnects through solder interconnects, creating a three-dimensional coupling architecture that reduces impedance and voltage droop while maintaining manufacturing feasibility.
2Reliability
If side wall coupling is implemented to reduce impedance and voltage droop, then PDN performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is prepared in advance with formed interconnects that have side walls positioned at specific locations. Cavities are created in the substrate, and the capacitor is placed within these cavities such that its terminals align with the pre-formed interconnect side walls. This preliminary preparation of the substrate structure simplifies the subsequent coupling process and enables automated assembly.
3Reliability
If capacitors are embedded partially within the substrate using side wall coupling, then impedance is reduced by 34%, but the substrate structure complexity increases
Solution Approach 1:
The capacitor is partially embedded within cavities of the substrate, with the capacitor body nested inside the substrate cavity and the terminals extending outward to couple with the interconnect side walls. This nesting arrangement achieves close proximity coupling for low impedance while containing the capacitor within the substrate structure, minimizing overall space requirements.
Data Source
AI summary
A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.