Embedded Multilayer Capacitor for Low Parasitic Inductance
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Solution Overview
Problem
Conventional decoupling capacitors introduce parasitic inductance and occupy valuable space, leading to increased impedance and costs in digital circuits, while embedded capacitors are costly and cumbersome to form.
Innovation Solution
A multilayer capacitor is integrated between the die and substrate, utilizing vias for interconnects to reduce parasitic inductance and occupy otherwise wasted space, thereby enhancing density and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are mounted to the package substrate or circuit board, then capacitance is provided for power smoothing, but parasitic inductance increases and valuable substrate space is occupied
Solution Approach 1:
The patent merges the decoupling capacitor with the package substrate by embedding the capacitor directly into the substrate structure. The capacitor is formed between substrate layers, eliminating the need for separate discrete capacitor components while providing the required power smoothing function. This integration reduces parasitic inductance by removing long external interconnect paths.
Solution Approach 2:
The capacitor is nested within the substrate structure itself, with capacitor plates formed between substrate layers. The capacitor is contained within the substrate volume, utilizing the substrate's internal space rather than occupying external substrate surface area or requiring separate mounting space.
2Object-affected harmful factors
If decoupling capacitors are integrated into the die, then parasitic inductance is reduced, but die density decreases and manufacturing costs increase
Solution Approach 1:
The patent combines the capacitor with the package substrate rather than integrating it into the die. The capacitor is formed using substrate layers and interconnect structures, separating the capacitor function from the die while maintaining close proximity to the die for low inductance. This approach preserves die density by not occupying die area.
Solution Approach 2:
The capacitor is implemented in the substrate dimension rather than on the die surface. By utilizing the substrate's vertical and lateral dimensions, the capacitor provides low inductance performance without consuming valuable die area, effectively moving the capacitor implementation to a different spatial dimension.
3Object-affected harmful factors
If embedded passive capacitors are formed using cavity embedding, then capacitance is provided with reduced inductance, but manufacturing complexity and cost increase
Solution Approach 1:
The capacitor is merged with the substrate manufacturing process itself, with capacitor plates formed between substrate layers during normal substrate fabrication. This eliminates the need for separate cavity formation and embedding steps, reducing manufacturing complexity while achieving low inductance performance.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical interconnection, and houses the embedded capacitor. The substrate layers serve both as structural elements and as capacitor plates, eliminating the need for separate capacitor components and simplifying the manufacturing process.
4Quantity of substance
If multilayer capacitor is placed between die and substrate, then capacitance density is increased and parasitic inductance is reduced, but package height may increase
Solution Approach 1:
The multilayer capacitor is nested within the substrate structure, with capacitor layers formed between substrate layers. The capacitor utilizes the substrate's internal volume rather than adding external height, effectively hiding the capacitor within the substrate's existing dimensional envelope.
Solution Approach 2:
The capacitor is implemented in the lateral and vertical dimensions of the substrate rather than adding height in the vertical direction. By utilizing the substrate's planar area and internal layering, the capacitor achieves high capacitance density without increasing the overall package height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer capacitor design significantly reduces parasitic inductance and increases capacitance density without contributing to the overall package height, making it a cost-effective alternative to conventional capacitors.
Implementation Method 1
a first metal layer, a second metal layer, and a dielectric layer intervening between the first metal layer and the second metal layer
Data Source
AI summary
A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.