Embedded Capacitor Substrate Design for Signal Integrity
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Solution Overview
Problem
Manufacturing a package for an electronic device that includes a capacitor embedded within the substrate layers to improve signal transmission and increase capacitor density while reducing costs.
Innovation Solution
A substrate is configured with capacitive material segmented into sections, directly coupled to conductors, and embedded within dielectric material layers, allowing for efficient signal transmission and increased capacitor density by reducing signal loss and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If capacitors are surface-mounted on the package exterior, then ease of manufacture is improved, but capacitor density and signal transmission performance deteriorate
Solution Approach 1:
The patent transitions from two-dimensional surface mounting to three-dimensional embedding within substrate layers. Capacitors are formed by depositing conductive and dielectric materials through multiple layers (first conductor layer, first dielectric layer, second conductor layer) within the substrate, utilizing vertical stacking to achieve higher density while maintaining manufacturing feasibility through standard semiconductor fabrication processes
2Ease of manufacture
If capacitors are surface-mounted on the package exterior, then ease of manufacture is improved, but signal transmission quality deteriorates
Solution Approach 1:
By embedding capacitors within the substrate layers rather than mounting on the surface, the patent reduces the path length for signal transmission and minimizes exposure to external noise and interference. The capacitors are surrounded by dielectric material that provides electrical isolation and shielding, improving signal integrity while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The capacitor structure is nested within the substrate layers, with conductive and dielectric materials embedded sequentially. The first conductor, first dielectric, and second conductor are layered within the substrate, creating a nested configuration that protects the capacitor from external interference and reduces signal loss while maintaining ease of manufacture through integrated fabrication
3Quantity of substance
If capacitors are embedded within substrate layers, then capacitor density and signal transmission quality are improved, but device complexity increases
Solution Approach 1:
The capacitor fabrication process is segmented into distinct sequential steps: depositing the first conductor layer, depositing the first dielectric layer, depositing the second conductor layer, and removing portions of these layers to form the capacitor structure. This segmentation allows complex embedded capacitor formation to be achieved through manageable, standardized fabrication steps, reducing overall device complexity
Solution Approach 2:
The patent uses standard semiconductor fabrication processes (physical vapor deposition, chemical vapor deposition, spin coating, photolithography, etching) that are already universally employed in the industry. By utilizing existing multi-functional equipment and processes for capacitor formation, the patent avoids introducing specialized manufacturing steps, thereby maintaining device complexity at acceptable levels while achieving high capacitor density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded capacitor design enhances the performance of electronic devices by reducing signal loss and noise, increasing capacitor density, and lowering production costs compared to surface-mounted capacitors.
Implementation Method 1
a first layer (140) including a capacitive material segmented into a first section (140A), and a second section (140B)
Data Source
AI summary
A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.