Embedded Thin-Film Capacitor Substrate for Vertical Power Delivery

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Solution Overview

Problem

Existing flip chip packages face challenges with RC signal delays and poor device density due to the use of decoupling capacitors with lateral power delivery and signal routing, which limits the effectiveness of noise filtering and power delivery.

Innovation Solution

The integration of thin-film capacitors within the package substrate core for vertical power delivery, allowing for embedded capacitors to form part of the substrate core and providing vertical connections for power delivery and noise filtering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If decoupling capacitors with lateral power delivery are used in flip chip packages, then noise filtering capability is improved, but RC signal delays increase and device density decreases

Engineering Contradiction:
Improvenoise filtering capabilityVSAvoidRC signal delays
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from lateral (2D) power delivery through decoupling capacitors to vertical (3D) power delivery through the substrate core. The substrate core is reconfigured to include vertical interconnects that deliver power directly from the bottom side to the top side, eliminating the need for lateral signal routing through decoupling capacitors and reducing RC delays while maintaining noise filtering capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent inverts the traditional power delivery approach by placing power delivery paths vertically through the substrate core rather than laterally on the surface. The substrate core is transformed from a passive support structure to an active power delivery medium with embedded vertical interconnects, reversing the conventional horizontal routing paradigm.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If decoupling capacitors are placed on the surface of the package, then noise filtering is achieved, but device density is reduced

Engineering Contradiction:
Improvenoise filteringVSAvoiddevice density
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent embeds the power delivery and noise filtering functionality within the substrate core itself, nesting the interconnect structures inside the substrate volume rather than placing components on the surface. The substrate core contains embedded vertical interconnects that provide both power delivery and decoupling functionality, eliminating the need for separate surface-mounted capacitors and increasing device density.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The substrate core is designed to perform multiple functions simultaneously: mechanical support, electrical interconnection, power delivery, and noise filtering. The vertical interconnects embedded in the substrate core provide both power delivery paths and decoupling capacitor functionality, eliminating the need for separate dedicated noise filtering components and maximizing space utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Power

If lateral signal routing through decoupling capacitors is used, then power delivery is achieved, but RC signal delays increase

Engineering Contradiction:
Improvepower deliveryVSAvoidRC signal delays
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent changes the routing dimension from lateral (horizontal) to vertical, creating direct through-substrate power delivery paths. The vertical interconnects provide short, direct routes for power delivery from the bottom side to the top side of the substrate, minimizing the length of current paths and reducing RC time constants compared to lateral routing through decoupling capacitors.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12334455B2Semiconductor package with integrated capacitors
Publication Date: 2025.06.17 CHIPLETZ INC
  • US12334455B2 patent drawing
  • US12334455B2 patent drawing
  • US12334455B2 patent drawing

AI summary

In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.