3D Embedded Capacitor via High-Aspect Ratio Vias
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Solution Overview
Problem
Modern semiconductor packages face challenges in reducing substrate thickness and surface-area footprint due to the limitations of embedding passive devices, particularly with glass substrates prone to micro-cracks from drilling and the impracticality of conventional capacitors in thin substrates.
Innovation Solution
A 3D embedded capacitor is formed within a dielectric-filled window in the substrate, utilizing a metal-insulator-metal (MIM) structure that lines vias extending through the substrate, providing increased capacitance without the need for surface mounting or substrate cavities, by exploiting high-aspect ratio vias that enhance the surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional surface-mount capacitors are mounted on the substrate, then capacitance is provided, but the substrate surface area increases and footprint increases
Solution Approach 1:
The capacitor structure transitions from a conventional 2D surface-mount configuration to a 3D embedded structure by utilizing vertical vias that extend through the substrate thickness. The metal-insulator-metal capacitor is formed within the substrate volume rather than on the surface, effectively using the third dimension (substrate thickness) to provide capacitance without increasing the substrate footprint.
2Length of stationary object
If substrates are thinned to reduce device profile, then thinner devices are achieved, but there is insufficient room to embed conventional passive devices
Solution Approach 1:
The capacitor geometry is changed from a conventional planar configuration to a vertical via-based structure. By utilizing the full substrate thickness for via formation and positioning the capacitor electrodes on the via surfaces, the design adapts to thin substrates by efficiently using the available vertical space rather than requiring additional lateral or depth space.
3Reliability
If SMT passive components are mounted on glass substrates, then capacitance is provided, but micro-cracks occur in the glass from drilling holes and vias
Solution Approach 1:
The harmful drilling process is eliminated by forming vias through alternative methods such as laser drilling or etching, which do not generate the mechanical stresses that cause micro-cracks in glass substrates. The via formation process is extracted from the conventional mechanical drilling approach and replaced with a method suitable for glass substrates.
4Ease of manufacture
If conventional 2D capacitors are used, then manufacturing is straightforward, but capacitance density per footprint area is limited
Solution Approach 1:
The capacitor structure utilizes the vertical dimension by forming vias through the substrate and positioning electrodes on the via surfaces. This 3D configuration increases the effective electrode surface area available for capacitance formation without proportionally increasing the substrate footprint, thereby improving capacitance density while maintaining manufacturing feasibility through established via formation and electrode deposition processes.
Data Source
AI summary
An embedded capacitor is provided that includes a substrate having a dielectric-filled window. A metal-insulator-metal structure lines a plurality of vias extending through the dielectric-filled window and covers at least partially opposing sides of the dielectric-filled window.