Embedded Capacitor Wiring Structure Using Damascene Process
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with capacitors require additional photolithography processes, which complicates the process and makes it difficult to form capacitors with a high degree of freedom in lead wiring structure without increasing the complexity of the manufacturing steps.
Innovation Solution
A semiconductor device and manufacturing method where a capacitor is formed with a lower electrode made of the same material as the conductive member, embedded in a capacitor recess, and the capacitor dielectric film covers the inner surface of a concave portion on the upper surface of the lower electrode, allowing the upper electrode to be embedded within this concave portion, without requiring additional photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If additional photolithography processes are used to form capacitors, then capacitor formation is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the capacitor formation process with the existing wiring formation process by using the same photolithography and etching steps. The capacitor electrodes are formed as part of the wiring pattern, eliminating the need for separate photolithography processes dedicated to capacitor formation.
Solution Approach 2:
The patent makes the wiring structure serve multiple functions: it acts as both the wiring interconnect and the capacitor electrode. The lower electrode is formed using the same conductive material and process steps as the wiring, allowing a single structure to fulfill both wiring and capacitor electrode functions.
2Ease of manufacture
If capacitor structure is added to existing wiring, then capacitor functionality is achieved, but lead wiring structure freedom is limited
Solution Approach 1:
The patent segments the capacitor structure into distinct functional regions (lower electrode, dielectric layer, upper electrode) that can be independently configured. This allows the lead wiring to connect to different parts of the capacitor structure (lower electrode, upper electrode, or side walls) providing flexibility in lead wiring arrangement.
Solution Approach 2:
The patent extends the capacitor structure into the vertical dimension with the lower electrode extending to the bottom surface and the upper electrode positioned at different heights. This three-dimensional configuration allows lead wirings to approach and connect to the capacitor from multiple directions and levels, increasing structural freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of capacitors without adding new photolithography steps, enabling a high degree of freedom in lead wiring structure and improving manufacturing reproducibility by adjusting the thickness of the lower conductive film to control the width of the capacitor's lower electrode.
Implementation Method 1
a lower conductive film is deposited under a condition that the first wiring trench and the first via hole are fully filled with the lower conductive film
Data Source
AI summary
A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion.