Embedded Capacitor in Multi-Layer Wiring for Semiconductor Integration
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Solution Overview
Problem
The integration of logic and memory circuits on the same semiconductor substrate poses challenges due to the need for different design parameters and increased complexity in manufacturing, particularly with the presence of capacitive elements, which affect capacitance and parasitic resistance, leading to reduced operation speed and increased manufacturing difficulty.
Innovation Solution
A semiconductor device with a multi-layered wiring structure that embeds a capacitive element, using at least two or more wiring layers between the lower and upper capacitor wirings, allowing for compact design without altering the logic circuit wiring structure, and utilizing copper wiring for low resistance and compatible design parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked capacitive element structure is used to ensure desired capacitance, then the capacitance is improved, but the contact height from the first wiring layer to the diffusion layer increases, increasing manufacturing difficulty
Solution Approach 1:
The patent applies dimensionality change by transitioning from a vertical stacked capacitive element structure to a planar embedded structure where the capacitive element is formed within the wiring layer itself. This allows the capacitive element to be integrated in the same plane as the logic circuit wiring, eliminating the need for increased contact height while maintaining the desired capacitance through optimized planar geometry and material selection.
Solution Approach 2:
The patent merges the capacitive element structure with the wiring layer structure, forming the capacitive element directly within the wiring layer rather than as a separate stacked component. This integration allows the capacitive element to share the same fabrication process and structural framework as the logic circuit wiring, reducing manufacturing complexity while maintaining functional performance.
2Reliability
If the height of the capacitive element is increased to ensure capacitance, then the capacitance is improved, but the distance between lower and upper capacitor wirings increases, increasing parasitic resistance
Solution Approach 1:
The patent eliminates the vertical stacking dimension by forming the capacitive element in a planar configuration within the wiring layer. This dimensional change reduces the distance between capacitor terminals by eliminating the need for tall vertical structures, thereby reducing parasitic resistance while maintaining capacitance through optimized planar electrode geometry and high-dielectric-constant materials.
Solution Approach 2:
The patent changes the geometric parameters of the capacitive element from vertical stacking to planar embedding, and adjusts material parameters by using high-dielectric-constant materials to achieve the desired capacitance with reduced dimensions. This parameter optimization allows sufficient capacitance to be achieved without increasing the distance between capacitor wirings, thus minimizing parasitic resistance.
3Reliability
If a trench type capacitive element is used with deep grooves, then the capacitance is improved, but the manufacturing process complexity increases extremely
Solution Approach 1:
The patent merges the capacitive element formation process with the existing wiring layer fabrication process. By forming the capacitive element within the wiring layer using the same deposition and patterning steps, the manufacturing process complexity is significantly reduced compared to separate deep trench formation processes, while still achieving the required capacitance through integrated structure design.
Solution Approach 2:
The patent transitions from deep vertical trench structures to shallow planar structures within the wiring layer. This dimensional change eliminates the need for complex deep groove formation processes while maintaining capacitance through optimized planar electrode configurations and high-dielectric-constant materials, thereby simplifying the manufacturing process.
4Productivity
If logic circuit and memory circuit are formed over the same semiconductor substrate, then the integration efficiency is improved, but different design parameters are needed for capacitive elements, increasing design complexity
Solution Approach 1:
The patent achieves universality by designing the capacitive element structure to be compatible with the standard logic circuit wiring layer structure. The embedded capacitive element uses the same wiring layer materials and fabrication processes as the logic circuit, allowing a single set of design parameters and manufacturing processes to serve both memory and logic circuit functions on the same substrate.
Solution Approach 2:
The patent merges the capacitive element design with the logic circuit wiring design, allowing both functions to share the same structural framework and design parameters. This integration enables simultaneous optimization of both memory and logic circuit performance without requiring separate design methodologies, thereby maintaining high integration efficiency while reducing design complexity.
Data Source
AI summary
Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.