Embedded Capacitor Wiring Substrate for Inductance Reduction
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Solution Overview
Problem
The lengthening of wiring lines connecting chip capacitors and IC chips in conventional wiring substrates leads to increased inductance, which fails to reliably reduce noise and stabilize power supply voltage.
Innovation Solution
A component-incorporated wiring substrate design where a second capacitor is embedded within the wiring laminate portion, reducing the length of wiring lines and preventing an increase in inductance, with a first capacitor accommodated in an accommodation hole portion and a component-mounting region for efficient power supply and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip capacitors are mounted on the front surface or back surface of the wiring substrate, then the power supply system can support multiple circuit sections, but the wiring lines become long and inductance increases
Solution Approach 1:
The patent embeds chip capacitors within recesses formed on the wiring substrate, nesting the capacitors into the substrate structure rather than mounting them on the surface. This integration shortens the wiring lines connecting the capacitors to the IC chip while maintaining the ability to support multiple circuit sections with separate power supply systems
Solution Approach 2:
The patent transitions from two-dimensional surface mounting to three-dimensional embedding by forming recesses in the substrate and placing capacitors within them. This dimensional change allows the capacitors to be positioned closer to the IC chip, reducing wiring line length and inductance while preserving power supply versatility
2Reliability
If chip capacitors are mounted on the surface of the wiring substrate, then the power supply voltage can be stabilized, but the inductance component of wiring increases and noise reduction becomes unreliable
Solution Approach 1:
By nesting chip capacitors into recesses within the wiring substrate, the patent minimizes the distance between capacitors and the IC chip. This reduces the inductance of connecting wiring lines, ensuring reliable noise reduction and power supply voltage stabilization without the harmful effects of long wiring
3Quantity of substance
If a via-array-type capacitor is incorporated in the wiring substrate, then high capacitance with small size is achieved, but the processor core and various circuit sections cannot be operated sufficiently
Solution Approach 1:
The patent uses multiple chip capacitors distributed at different locations on the wiring substrate, each serving specific circuit sections. This segmentation allows the processor core and various circuit sections to have dedicated power supply capacitors, enabling sufficient operation of each section while maintaining high capacitance density through the via-array-type incorporated capacitor
Data Source
AI summary
An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.