Embedded Demultiplexer CDR for Low-Latency Jitter Tracking
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Solution Overview
Problem
Conventional digital clock and data recovery (CDR) circuits face high latency issues that hinder their ability to scale with increasing input datastream frequencies, particularly at 10 Gbps or higher, leading to unstable loop behavior and reduced jitter tolerance.
Innovation Solution
A low latency high bandwidth CDR architecture is implemented by embedding CDR operations into a demultiplexer, including a partially or fully embedded phase error processor and digital loop filter, allowing for granular mixed signal implementations that reduce overall latency and enhance jitter tolerance at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If loop bandwidth is increased to track higher frequency jitter, then jitter tracking accuracy is improved, but loop stability deteriorates due to high latency
Solution Approach 1:
The patent segments the CDR functionality by separating the high-speed data path (through the demultiplexer) from the phase error processing path. This segmentation allows the data to be rapidly demultiplexed with minimal latency while phase errors are processed separately, enabling higher loop bandwidth without compromising stability.
Solution Approach 2:
The patent introduces a new architectural dimension by embedding CDR operations within the demultiplexer structure itself, rather than treating them as separate sequential stages. This dimensional reorganization allows parallel processing of data demultiplexing and phase error detection, effectively reducing the time dimension (latency) of the critical path.
2Loss of time
If overall latency is decreased to enable higher loop bandwidth, then jitter tolerance is improved, but reliability deteriorates due to susceptibility to process, voltage and temperature variations
Solution Approach 1:
The patent replaces traditional analog CDR mechanisms with a digital implementation that embeds phase error processing within the demultiplexer. This substitution allows for precise digital control of latency while maintaining reliability through the robustness of digital logic against PVT variations.
Solution Approach 2:
The patent merges the CDR functionality with the demultiplexer structure, combining what were previously separate functions into a unified architecture. This merging eliminates the need for separate high-speed data paths and phase processing paths, reducing overall latency while maintaining reliability through integrated design.
3Ease of manufacture
If conventional digital CDR is used for flexibility and simplicity, then ease of manufacture is improved, but latency increases making it unsuitable for high frequency applications
Solution Approach 1:
The patent creates a universal architecture where the demultiplexer simultaneously performs its traditional data distribution function and embedded CDR operations. This multi-functionality maintains the simplicity and flexibility of digital implementation while dramatically reducing latency by eliminating separate CDR processing stages.
Data Source
AI summary
Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.