Embedded Chip Package Structure for Shorter 3D Interconnect Paths
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Solution Overview
Problem
The reliability of electrical connections between conductive terminals and internal components in semiconductor packages is a challenge due to the complexity of 3D packaging and integration in semiconductor devices, where existing technologies face difficulties in ensuring consistent and efficient communication paths between stacked semiconductor chips.
Innovation Solution
A method of fabricating a chip structure that includes embedding a second semiconductor chip within a first semiconductor chip, surrounded by conductive vias and a redistribution layer, which electrically connects the chips, and further integrating these structures with a package structure using a redistribution layer and insulating encapsulant to enhance communication paths and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 3D packaging and integration are implemented to increase device functionality, then the quantity of components and integration density improve, but the reliability of electrical connections between conductive terminals and internal components deteriorates
Solution Approach 1:
The patent embeds a second semiconductor chip within a first semiconductor chip, creating a nested structure where one device is placed inside another. This nesting approach increases integration density while maintaining reliable electrical connections through conductive vias that penetrate through the first chip to connect to the second chip's terminals, avoiding the need for complex external interconnections.
Solution Approach 2:
The patent transitions from planar 2D packaging to 3D vertical integration by stacking semiconductor chips in the thickness direction. Conductive vias extend vertically through the first chip to establish electrical connections with the second chip embedded within, utilizing the third dimension (depth/height) to achieve higher integration while preserving connection reliability through direct vertical pathways.
2Adaptability or versatility
If communication paths between stacked semiconductor chips are extended, then more chips can be integrated, but the transmission efficiency and signal quality deteriorate
Solution Approach 1:
The patent creates localized high-quality electrical connections through conductive vias that provide direct, short transmission paths between chips. Rather than relying on long external interconnects, the vias establish concentrated, low-resistance pathways locally within the package structure, maintaining signal integrity even as more chips are stacked and integrated.
3Ease of manufacture
If complex packaging structures are used to achieve wafer-level integration, then manufacturing capability increases, but the difficulty of ensuring consistent electrical connections worsens
Solution Approach 1:
The patent performs preliminary processing of conductive vias and terminal structures on wafers before dicing and final assembly. By pre-forming the electrical connection structures at the wafer level and then embedding completed chips, the method ensures consistent connection geometry and reduces variability, making manufacturing easier while maintaining precision.
Data Source
AI summary
A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.