Embedded Chip Package Assembly With Bidirectional Heat Dissipation

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Solution Overview

Problem

The increasing integration of chips in electronic devices leads to a serious heat dissipation problem, posing a safety hazard due to ineffective heat management.

Innovation Solution

A chip package assembly design featuring a package substrate with upper and lower conductive layers and a conductive part surrounding the chip, allowing bidirectional heat dissipation through front and back electrodes, combined with a heat dissipation part connected to the upper conductive layer, enhancing heat exchange.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If chip integration density is increased, then device compactness is improved, but heat dissipation performance deteriorates

Engineering Contradiction:
Improvedevice compactnessVSAvoidheat dissipation performance
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The patent transitions from traditional single-direction heat dissipation to three-dimensional bidirectional heat dissipation by connecting both the front electrode and back electrode of the chip to conductive layers, enabling heat to be conducted in multiple spatial directions simultaneously

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The heat dissipation function is divided into multiple independent pathways: front electrode to lower conductive layer, back electrode to upper conductive layer, and heat dissipation part connected to upper conductive layer, allowing heat to be dissipated through parallel channels

Inventive Principle:
Principle #1Segmentation

2Device complexity

If traditional single-direction heat dissipation is used, then structure is simple, but heat dissipation efficiency is insufficient

Engineering Contradiction:
Improvestructure simplicityVSAvoidheat dissipation efficiency
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The conductive layers serve dual functions: they provide electrical connection for signal transmission and simultaneously act as heat conduction pathways, eliminating the need for separate heat dissipation structures and maintaining structural simplicity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the heat dissipation function with the existing electrical connection structure by using the conductive layers and electrodes for both purposes, avoiding additional complex components

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves effective heat dissipation, improving safety by reducing the risk of damage from heat buildup and providing electromagnetic shielding, moisture-proofing, and structural stability.

Implementation Method 1

the upper conductive layer, the lower conductive layer, and the conductive part each are characterized by a coefficient of thermal conductivity. It can be understood that the conductive part, the lower conductive layer, and the upper conductive layer each have a coefficient of thermal conductivity sufficient to effectively conduct heat generated by the chip

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The heat dissipation part is connected to a surface of the upper conductive layer that is away from the chip. It can be understood that compared with the upper conductive layer, the heat dissipation part has a larger heat exchange surface area, and therefore has a relatively strong heat dissipation function

Methodology Applied
Scientific EffectHeat exchange: Heat Exchanger

Data Source

PatentUS12354967B2Chip package assembly, electronic device, and preparation method of chip package assembly
Publication Date: 2025.07.08 HUAWEI TECH CO LTD
  • US12354967B2 patent drawing
  • US12354967B2 patent drawing
  • US12354967B2 patent drawing

AI summary

This application discloses a chip package assembly, an electronic device, and a preparation method of a chip package assembly. The chip package assembly includes a package substrate, a chip, and a heat dissipation part. The package substrate includes an upper conductive layer, a lower conductive layer, and a conductive part connected between the upper conductive layer and the lower conductive layer. The chip includes a front electrode and a back electrode that are disposed opposite each other, the chip is embedded in the package substrate, the conductive part surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. The heat dissipation part is connected to a surface of the upper conductive layer that is away from the chip. The upper conductive layer, the lower conductive layer, and the conductive part each conduct heat.