Embedded Semiconductor Chip Carrier Board with Through Trenches
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Solution Overview
Problem
Conventional semiconductor package fabrication methods face challenges such as reduced usable space on carrier boards, unbalanced stresses leading to warpage, low product yield, increased production costs, and extended shaping times due to inefficient cutting processes and copper circuit extensibility.
Innovation Solution
The method involves forming through openings and trenches on a carrier board, embedding semiconductor chips with dielectric layers, and creating conductive vias and circuit layers to enable direct electrical connections, while using a metallic board to balance stresses and facilitate efficient cutting through trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple semiconductor chips are embedded in a carrier board using conventional methods, then production cost is reduced, but usable layout space on the carrier board is reduced due to space required for cutting processes
Solution Approach 1:
The patent divides the carrier board into multiple regions with through openings for chip embedding and dedicated cutting regions separated by grooves. This segmentation allows independent optimization of chip placement space and cutting space, enabling efficient use of the carrier board area while maintaining cost-effective mass production capabilities.
Solution Approach 2:
The patent introduces grooves that extend from the front surface to the back surface of the carrier board, creating a three-dimensional separation structure. This dimensional approach allows cutting paths to be defined in advance without occupying lateral space on the carrier board surface, thereby preserving usable layout space while enabling efficient post-processing separation.
2Device complexity
If circuit patterning is performed on only one surface of the substrate, then manufacturing process is simplified, but unbalanced stresses cause warpage of the carrier board
Solution Approach 1:
The patent employs asymmetric groove positioning and depth control to balance stresses during circuit patterning. The grooves are strategically placed and sized to provide stress relief on the patterned surface while maintaining overall carrier board flatness, enabling single-sided patterning without warpage issues.
Solution Approach 2:
The grooves act as stress-compensating features that counterbalance the stresses induced by circuit patterning on one surface. By creating controlled voids or relief regions, the grooves provide mechanical counterweight that prevents warpage while allowing simplified single-sided manufacturing processes.
3Productivity
If direct cutting on the carrier board is performed, then shaping time cannot be decreased, but copper circuits may be scratched causing package damage
Solution Approach 1:
The patent pre-forms grooves during the carrier board fabrication process before any cutting operations. These grooves serve as predetermined cutting paths that guide subsequent separation operations, allowing fast cutting without risking damage to copper circuits or packages since the cutting path is already established and protected by the groove structure.
Data Source
AI summary
An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.