Embedded Chip Package Using Photosensitive Dielectric Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip packaging methods using thermosetting polymers face challenges such as damage from laser drilling and low efficiency in dry etching, particularly for high aspect ratio conduction posts and small openings, leading to poor heat dissipation and electrical conduction performance.
Innovation Solution
The use of photosensitive polymer dielectric materials, such as polyimide and polyphenylene oxide resins, to fill gaps between chips and frames, allowing for direct formation of via-posts and wiring layers through photolithography and electroplating, which enhances heat dissipation and electrical connectivity without damaging the chip structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser drilling is used to form openings in thermosetting polymer packaging material, then electrical connection and heat dissipation can be achieved, but the high laser energy may damage the chip structure or break down thin conduction terminals
Solution Approach 1:
The patent changes the material parameter from thermosetting polymer to photosensitive polymer dielectric, which allows for lower energy processing. The photosensitive material can be patterned and removed at lower energy levels compared to laser drilling through cured epoxy, thereby protecting thin conduction terminals while still achieving the required openings for electrical connection and heat dissipation.
Solution Approach 2:
The patent replaces the mechanical/thermal laser drilling process with a photolithography-based chemical removal process. Instead of using high-energy laser beams that mechanically ablate material, the invention uses photoresist patterns and chemical etchants to selectively remove the photosensitive polymer dielectric, achieving the same opening formation function with much lower energy input that protects delicate chip structures.
2Reliability
If plasma dry etching is used to form large openings in packaging material, then both sides of the chip can be connected, but the etching time becomes extremely long (50-150 minutes) reducing production efficiency
Solution Approach 1:
The patent changes the packaging material parameter to photosensitive polymer dielectric, which enables much faster removal rates compared to plasma dry etching of thermosetting polymers. The photosensitive material can be selectively removed through photolithography and chemical development processes that complete in minutes rather than hours, achieving the same two-sided connection function with dramatically improved production efficiency.
Solution Approach 2:
The patent replaces the slow plasma dry etching process with a photolithography-based chemical removal process. The photosensitive polymer dielectric can be patterned and removed using standard photolithography tools and chemical developers, achieving rapid opening formation for both sides of the chip without the time-consuming plasma etching steps, thus greatly improving productivity while maintaining reliable electrical connection.
3Manufacturing precision
If plasma dry etching is used to form small vias in packaging material, then electrical connection can be achieved, but the low gas exchange rate in small vias further decreases etching rate and produces poor via quality
Solution Approach 1:
The patent changes the packaging material to photosensitive polymer dielectric, which enables superior via formation for small diameter vias. The photolithography process can precisely define small via openings with excellent roundness and dimensional control, while the chemical development process provides uniform removal rates regardless of via depth or diameter, achieving both high manufacturing precision and good productivity that plasma etching cannot match for small via dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, improves production efficiency, reduces costs, and prevents damage to chips, while providing excellent adhesion and thermal management, enabling effective heat dissipation and electrical conduction without exposing glass fibers, thus enhancing the reliability and yield of chip packages.
Implementation Method 1
a photosensitive polymer dielectric material is used as the packaging material, allowing for direct formation of via-posts and wiring layers through photolithography
Implementation Method 2
direct formation of via-posts and wiring layers through photolithography and electroplating
Data Source
AI summary
Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.