Embedded Chip Packaging With Dual Heat Paths and Flush Interconnects

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Solution Overview

Problem

Existing advanced packaging technologies for high-bandwidth memory chips face issues with limited I/O speed, high power consumption, complex processes, high costs, and inadequate heat dissipation due to the presence of interposers and silicon bridges, which affect the efficiency and reliability of electrical connections.

Innovation Solution

A packaging structure with a first chip embedded in a substrate cavity, utilizing independent heat-conducting channels through a first and second heat conductor, and flush connecting surfaces for improved electrical stability and heat dissipation, combined with a laminated plate and metal foil laminate for enhanced bonding and heat management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an interposer and silicon bridge are used for connection, then electrical connection between chips is achieved, but I/O speed is limited and power consumption increases

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the interposer and silicon bridge from the packaging structure, directly connecting chips to the package substrate. This extraction of unnecessary intermediary components reduces power consumption while maintaining electrical connection reliability through direct bonding interfaces.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If TSV process is used for 2.5D packaging, then high-density interconnection is achieved, but manufacturing cost increases

Engineering Contradiction:

Improveinterconnection densityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive TSV processes with simpler, more cost-effective bonding techniques. By using direct chip-to-substrate bonding without requiring through-silicon via fabrication, the manufacturing cost is significantly reduced while maintaining adequate interconnection density for the application.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Reliability

If RDL is used for interconnection, then wiring density is increased, but the process becomes more complex

Engineering Contradiction:

Improvewiring densityVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent eliminates the RDL (redistribution layer) structure from the packaging design. By directly bonding chips to the package substrate with appropriate pad layouts, the need for complex multi-layer RDL fabrication is removed, simplifying the manufacturing process while maintaining necessary wiring density.

Inventive Principle:

Principle #2Taking out (Extraction)

4Reliability

If chip is laminated on package substrate, then electrical connection is achieved, but heat dissipation efficiency decreases

Engineering Contradiction:

Improveelectrical connectionVSAvoidheat dissipation efficiency

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The patent segments the heat dissipation function from the electrical connection function. By providing dedicated heat-conducting surfaces and separate heat dissipation pathways on the chips, heat can be efficiently extracted without interfering with the electrical bonding interfaces, thus improving heat dissipation while maintaining electrical connection reliability.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances heat dissipation efficiency and electrical connection reliability by using independent heat-conducting channels and flush connecting surfaces, improving packaging yield and reducing the impact of the package substrate on heat dissipation.

Implementation Method 1

a first heat conductor and a second heat conductor, the first heat conductor being connected to the first heat-conducting surface, and the second heat conductor being connected to the second heat-conducting surface

Methodology Applied

Scientific EffectHeat conduction: Conduction (thermal)

Implementation Method 2

the prepreg includes resin and is laminated such that the resin enters the cavity and fixes the first chip

Methodology Applied

Scientific EffectLamination: Lamination

Data Source

PatentUS12519022B2Packaging structure and manufacturing method thereof

Publication Date: 2026.01.06 JCET MANAGEMENT CO LTD

AI summary

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.