Embedded Chip Interconnect Bridge for High-Density I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging technologies, such as ceramic-based and organic laminate substrates, are limited in achieving high-density I/O flip-chip connections and die-to-die interconnections due to constraints on contact pad pitch, line width, and line spacing, and silicon interposers are expensive and complex, while existing silicon bridge devices do not support vertical power distribution effectively.
Innovation Solution
The implementation of multi-chip package structures with embedded chip interconnect bridges and fan-out redistribution layers, which provide high I/O interconnect density and vertical power distribution by using chip interconnect bridges embedded within a wafer-level or panel-level fan-out redistribution layer, allowing for efficient routing of power and ground connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ceramic-based or organic laminate substrates are used for MCM packaging, then manufacturing cost is reduced, but contact pad pitch, line width, and line spacing cannot achieve the tight pitches needed for high-density I/O flip-chip connections
Solution Approach 1:
The patent transitions from planar 2D substrate routing to 3D vertical interconnection through embedded silicon bridge devices with through-silicon vias (TSVs). This dimensional change enables tight pitch interconnections by routing signals vertically through the substrate thickness rather than laterally across the surface, achieving contact pad pitches of 50 microns or less while maintaining manufacturing feasibility.
Solution Approach 2:
The patent employs a composite substrate structure combining silicon bridge devices with organic laminate or ceramic substrates. The silicon bridges provide high-density vertical interconnects with TSVs, while the surrounding organic or ceramic material provides mechanical support and cost-effective manufacturing. This composite approach achieves both high precision and ease of manufacture.
2Manufacturing precision
If silicon interposers are used to achieve high wiring density and tight interconnect pitch, then I/O density is improved, but fabrication cost and device complexity increase significantly
Solution Approach 1:
The patent segments the interconnection function into two parts: embedded silicon bridge devices provide high-density vertical interconnects for critical I/O paths, while the surrounding organic laminate substrate handles less critical routing. This segmentation reduces overall device complexity by avoiding a complete silicon interposer, lowering fabrication costs while maintaining tight pitch where needed.
Solution Approach 2:
The patent uses embedded silicon bridge devices as intermediary elements within the organic laminate substrate. These silicon bridges act as localized high-density interconnect mediators rather than requiring a full silicon interposer, reducing complexity by integrating only where necessary and using the organic substrate for the remainder of the interconnection network.
3Productivity
If IC die functionality and density are increased to meet application requirements, then I/O count and I/O density increase, but voltage drop and IR heating increase
Solution Approach 1:
The patent uses vertical 3D interconnection through embedded silicon bridges with TSVs to reduce current path length. By routing power and ground connections vertically through the substrate rather than laterally across long distances, the resistance is reduced, minimizing voltage drop and IR heating while supporting higher I/O density.
Data Source
AI summary
A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.