Embedded Chip Circuit Board Layout for Low-Loss Thin PCBs
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Solution Overview
Problem
Circuit boards with densely distributed functional components face challenges in thinning due to multiple circuit layers acting as conductive paths, leading to signal losses and increased signal transmission noise.
Innovation Solution
A circuit board design with an embedded chip that includes a dielectric layer, a first circuit layer, a conductive connector, and an insulating protection layer, where the conductive connector contacts chip pads and a trace at the same level, reducing the number of boundaries for signal transmission and allowing for thinner board designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple circuit layers are used as conductive paths between functional components, then the circuit board can accommodate densely distributed components, but the circuit board thickness increases and signal losses occur due to increased boundaries
Solution Approach 1:
The chip is embedded within the dielectric layer of the circuit board, with the conductive connector integrating the chip pads directly with the circuit trace at the same level. This nesting approach allows the chip to be housed within the board structure rather than mounted on the surface, reducing overall thickness while maintaining component density
Solution Approach 2:
The invention transitions from traditional multi-layer vertical stacking to a planar integration approach where the chip and circuit trace coexist at the same level within the dielectric layer. This dimensional reorganization eliminates the need for additional circuit layers, achieving thinness while preserving functional connectivity
2Productivity
If multiple circuit layers are used to connect functional components, then component density is maintained, but signal losses increase due to increased number of boundaries current signals must pass through
Solution Approach 1:
The chip is nested within the dielectric layer with direct planar connection to the circuit trace, eliminating the need for vertical transitions through multiple dielectric layers and vias. This single-level integration reduces the number of boundaries current signals must cross, minimizing signal loss while maintaining dense component layout
Solution Approach 2:
The chip pads and circuit trace are merged at the same level within the dielectric layer, creating a continuous conductive path without intermediate boundaries. This merging eliminates signal reflections and losses associated with layer transitions, achieving low-loss signal transmission while supporting high component density
Data Source
AI summary
The present disclosure provides a circuit board with an embedded chip, which includes a dielectric layer, a first circuit layer, a chip, a conductive connector, and an insulating protection layer. The first circuit layer includes at least one first trace in the dielectric layer. The chip is in the dielectric layer and adjacent to the first trace, where the chip includes a plurality of chip pads at an upper surface of the chip. The conductive connector is on the upper surface of the chip and on the first circuit layer, where a lower surface of the conductive connector contacts at least one chip pad of the chip pads and an upper surface of the first trace. The insulating protection layer is on the chip, the first circuit layer, and the conductive connector, where the insulating protection layer contacts the upper surface of the chip.