Embedded Chip Package Compression Process
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Solution Overview
Problem
Conventional embedded chip package structures face a trade-off between increasing chip density and maintaining a compact size, as adding more chips requires a larger volume, which contradicts the trend of miniaturization and product streamlining.
Innovation Solution
The solution involves a method where chips are stacked between two substrates with patterned circuit layers, embedded within a dielectric material layer, using a flip-chip bonding process and a compression technique to reduce the overall size while accommodating more chips, utilizing a dielectric material like glass epoxy based resin to form a conductive through hole for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more chips are disposed on the circuit substrate, then the number of chips in the package structure is increased, but the carrying surface area and volume of the package structure must be increased
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of chips on the substrate surface to a three-dimensional embedded structure. Chips are embedded within the substrate volume at different depths and positions, utilizing the third dimension (depth/height) to accommodate more chips without increasing the substrate's footprint or overall volume significantly.
Solution Approach 2:
The patent embeds chips within the substrate structure, nesting them inside the substrate volume rather than placing them on the surface. Multiple chips are nested at different positions and depths within the substrate, allowing higher chip density while maintaining a compact package volume.
2Volume of moving object
If the embedded chip package structure is miniaturized, then the volume is reduced, but the number of chips that can be packed inside is reduced
Solution Approach 1:
By utilizing three-dimensional embedding within the substrate volume, the patent maximizes chip packing density. Chips are positioned at various depths and lateral positions within the substrate, effectively using the available volume in all three dimensions to accommodate more chips in a miniaturized package.
Solution Approach 2:
The patent employs selective embedding at different positions and depths within the substrate, optimizing the spatial distribution of chips. Different regions of the substrate utilize different embedding depths and configurations to maximize chip density while maintaining electrical connectivity and mechanical integrity.
Data Source
AI summary
An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.