Embedded Chip Package Conductive Lines for High-Density Interconnects
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Solution Overview
Problem
Current methods for producing through-encapsulant vias (TEVs) are limited by high costs, low via density, and design constraints due to the use of pre-produced via bars or laser drilling, which face challenges with inorganic filler particles and aspect ratios, leading to incomplete metal filling and interrupted connections.
Innovation Solution
A method for manufacturing embedded chip packages involving the formation of electrically conductive lines over a substrate, with insulating material surrounding them, and integrating these lines proximate to the chip's side wall, allowing for the creation of high-density vertical contacts between the chip's top and bottom sides using planar technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pre-produced via bars are used for through-encapsulant vias, then the manufacturing process is simple, but the via density is very limited and costs are high
Solution Approach 1:
The patent replaces the mechanical PCB via bar embedding process with a planar deposition process that forms conductive lines directly on the substrate. This substitution enables continuous conductive paths with much higher density while eliminating the need for discrete via bars, thereby resolving the contradiction between manufacturing simplicity and via density.
Solution Approach 2:
The patent changes the fundamental parameter of via formation from discrete embedded bars to continuous planar deposited lines. This parameter change allows for arbitrary pitch and high-density arrangements that were impossible with traditional via bars, while maintaining ease of manufacture through standard planar deposition techniques.
2Adaptability or versatility
If laser drilling is used to form holes for vias, then vias can be located everywhere, but the via diameter is large and via density is limited
Solution Approach 1:
The patent replaces laser drilling with planar deposition to form conductive lines. This substitution eliminates the minimum hole diameter constraint inherent in laser drilling, allowing for much finer feature sizes and higher via density while retaining the flexibility to place vias anywhere on the substrate.
Solution Approach 2:
The patent changes the formation method from subtractive (laser drilling) to additive (planar deposition). This parameter change enables arbitrary small dimensions for conductive lines, removing the lower diameter limit imposed by laser drilling while maintaining location flexibility.
3Adaptability or versatility
If laser drilling is used for via formation, then vias can be located everywhere, but inorganic filler particles cause undercuts and interrupted connections
Solution Approach 1:
The patent replaces laser drilling with planar deposition of conductive lines. This substitution eliminates the undercut problem caused by laser drilling through inorganic filler particles in encapsulant material, ensuring continuous and reliable connections while maintaining the ability to place vias anywhere on the substrate.
Solution Approach 2:
The patent uses planar deposition as an intermediary process that forms conductive lines without the harsh localized heating of laser drilling. This intermediary approach avoids the interaction between laser energy and inorganic filler particles that causes undercuts and connection interruptions.
4Length of moving object
If thick wafers are used with laser-drilled vias, then via height can be increased, but aspect ratio causes interrupted connections in seed layer
Solution Approach 1:
The patent replaces laser drilling with planar deposition to form conductive lines. This substitution eliminates the aspect ratio problem that occurs with thick wafers, as planar deposition can form continuous conductive paths regardless of substrate thickness, ensuring uninterrupted seed layer connections even for tall via structures.
Data Source
AI summary
A method (200) for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate (210); placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip (230); and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad (240).