Embedded Chip Package Interconnects for Double-Sided I/O
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Solution Overview
Problem
Current embedded chip build-up processes face challenges in achieving a double-sided I/O system for IC packages, leading to warpage and increased complexity and cost due to the need for multiple re-distribution layers and additional processing steps.
Innovation Solution
A method involving the fabrication of pre-fabricated interconnects with copper feed-through pads and metallization paths on insulating films, allowing for electrical connections between top and bottom surfaces, reducing the number of processing steps and maintaining package flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple re-distribution layers are applied to achieve a double-sided I/O system, then I/O connectivity is improved, but warpage occurs requiring stress balance layers or metal stiffeners
Solution Approach 1:
The patent divides the interconnection system into separate segments: through-substrate conductors embedded in the substrate, and conductor layers formed on the laminate. This segmentation allows the through-substrate conductors to provide mechanical support and electrical connection, while the conductor layers provide I/O connectivity, eliminating the need for multiple laminate layers and avoiding warpage.
Solution Approach 2:
The patent introduces through-substrate conductors as intermediary elements that penetrate the substrate to provide both mechanical support and electrical connection. These conductors act as mediators between the die and the external environment, enabling double-sided I/O without requiring multiple stress-prone laminate layers.
2Adaptability or versatility
If multiple re-distribution layers are applied to create double-sided I/O system, then I/O routing capability is improved, but the number of processing steps increases
Solution Approach 1:
The patent segments the interconnection function into through-substrate conductors (embedded in substrate) and conductor layers (formed on laminate). This segmentation allows each component to be optimized independently and simplifies the overall manufacturing process by eliminating multiple laminate deposition and patterning steps.
Solution Approach 2:
The through-substrate conductors are formed and embedded in the substrate before the laminate is applied. This preliminary action establishes the mechanical and electrical foundation early in the process, allowing subsequent conductor layers to be formed more simply on the laminate surface without requiring multiple complex lamination steps.
3Adaptability or versatility
If additional re-distribution layers are added to achieve double-sided I/O, then I/O system functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the interconnection system into through-substrate conductors and conductor layers on laminate. This segmentation eliminates the need for multiple expensive re-distribution layer laminations, reducing material costs and manufacturing complexity while maintaining double-sided I/O functionality.
Solution Approach 2:
The patent extracts the I/O routing function from the laminate structure and places it in conductor layers formed on the laminate surface. This extraction eliminates the need for multiple thick re-distribution layers, reducing material usage and manufacturing cost while achieving the desired double-sided I/O capability.
Data Source
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AI summary
An interconnect assembly (38) for an embedded chip package includes a dielectric layer (42), first metal layer comprising upper contact pads (52, 54), second metal layer comprising lower contact pads (56, 58), and metalized connections (62) formed through the dielectric layer (42) and in contact with the upper and lower contact pads (52-58) to form electrical connections therebetween. A first surface of the upper contact pads (52, 54) is affixed to a top surface of the dielectric layer (42) and a first surface of the lower contact pads (56, 58) is affixed to a bottom surface of the dielectric layer (42). An input/output (I/O) of a first side of the interconnect assembly (38) is formed on a surface of the lower contact pads (56, 58) that is opposite the first surface of the lower contact pads (56, 58), and an I/O of a second side of the interconnect assembly (38) is formed on a surface of the upper contact pads (52, 54) that is opposite the first surface of the upper contact pads (52, 54).