Embedded Chip Package Layout for Low-Inductance Power Delivery
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Solution Overview
Problem
Conventional chip packaging schemes face challenges in high-frequency performance due to intrinsic inductance and resistance in power and ground routings, which affect decoupling efficiency and destabilize the power delivery network, impacting IC die performance.
Innovation Solution
The integration of active and/or passive devices is embedded in series between the package substrate and the IC die, with one device in a first substrate and another in a second substrate stacked directly or in a common substrate, reducing routing loop inductance and enhancing proximity to the IC die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If decoupling capacitors are mounted on the top and/or bottom surface of the package substrate, then the package structure is simple and easy to manufacture, but the intrinsic inductance and resistance of the package substrate routing detrimentally affect decoupling efficiency at high frequencies
Solution Approach 1:
The patent transitions from surface-mounted capacitors (2D placement on package substrate) to embedded capacitors within the substrate thickness (3D integration). The capacitor is positioned inside the package substrate between the IC die and the substrate bottom surface, creating a vertical stacking arrangement that reduces horizontal routing distance and minimizes loop inductance while maintaining manufacturing feasibility through modified substrate fabrication processes.
Solution Approach 2:
The capacitor is nested within the package substrate structure itself, with the capacitor body embedded in the substrate material. The substrate acts as both the mounting platform and the housing for the capacitor, integrating two previously separate components into a single nested structure that reduces overall package size and routing complexity.
2Quantity of substance
If the integrated devices are embedded in a common package substrate, then the device density is increased, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the package substrate into multiple functional layers: a first region containing the embedded capacitor and a second region containing the TSV structure. This segmentation allows each region to be optimized independently for its specific function while maintaining overall integration, simplifying the manufacturing process by treating different device types as separate modular units within the same substrate.
Data Source
AI summary
A chip package and methods for fabricating the same are provided that include integrated devices embedded and coupled in series between a lower surface of a package substrate and an integrated circuit die of the chip package. In some examples, the integrated devices are disposed side by side embedded in a common package substrate. In other examples, one of the series coupled integrated devices is embedded in a first package substrate while another of the series coupled integrated devices is embedded in a second package substrate that is stacked directly in contact with the first package substrate. The integrated devices may be passive and/or active integrated devices.