Embedded Chip Semiconductor Package for Wafer and Panel Processing
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Solution Overview
Problem
Current semiconductor package fabrication processes are complex and costly, lacking compatibility with both wafer-level and panel-level package processes, which hinders efficiency and cost-effectiveness.
Innovation Solution
A semiconductor package design featuring a substrate with a redistribution layer, a semiconductor chip, and connection structures, integrated with a dielectric layer, allowing for simplified fabrication and compatibility with both wafer-level and panel-level package processes by using a carrier substrate and preliminary substrate with wafer or panel shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semiconductor package fabrication processes are used, then reliability and durability can be improved, but the fabrication process becomes complex and costly
Solution Approach 1:
The fabrication process is divided into distinct stages: forming connection structures on the substrate, building the dielectric layer with embedded semiconductor chips, and finally forming the redistribution layer. This segmentation allows each stage to be optimized independently while maintaining overall reliability.
Solution Approach 2:
Connection structures are formed on the substrate before the semiconductor chips are mounted. This preliminary action simplifies subsequent assembly steps and reduces fabrication complexity while ensuring reliable electrical connections are established in advance.
2Reliability
If traditional semiconductor package fabrication processes are used, then reliability and durability can be improved, but fabrication cost increases
Solution Approach 1:
Multiple functions are merged into the dielectric layer: it serves as both the insulating medium and the embedding matrix for semiconductor chips. This consolidation reduces the number of separate manufacturing steps and materials required, lowering fabrication costs while maintaining reliability.
Solution Approach 2:
The dielectric layer performs multiple functions simultaneously: electrical insulation, mechanical support for chips, and embedding medium for connection structures. This multi-functionality reduces overall package complexity and manufacturing cost while ensuring reliable operation.
3Ease of manufacture
If a simplified fabrication process is used, then fabrication cost is reduced, but compatibility with wafer-level and panel-level package processes is lost
Solution Approach 1:
The substrate is designed to serve multiple package types: it can function as a wafer substrate for wafer-level packaging or as a panel substrate for panel-level packaging. This universal design allows the same fabrication process to produce different package types, maintaining compatibility while reducing costs.
Solution Approach 2:
The fabrication process is designed to be adaptable and scalable: the same basic process steps can be applied whether packaging individual wafers or entire panels, allowing flexibility in production volume and package type while maintaining cost efficiency.
4Reliability
If connection structures are positioned close to the semiconductor chip, then electrical connection is improved, but interference between chip and connection structures increases
Solution Approach 1:
The dielectric layer acts as an intermediary medium between the semiconductor chip and connection structures. It provides electrical insulation while allowing controlled electrical connections through embedded conductive paths, reducing interference while maintaining connection reliability.
Solution Approach 2:
The dielectric layer has different properties in different regions: it provides insulation in areas where interference would occur, while allowing controlled conductivity where electrical connections are needed. This localized quality optimization resolves the contradiction between connection and interference.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a substrate including first and second surfaces opposite to each other, a redistribution layer on the first surface and having third and fourth surfaces opposite to each other wherein the third surface of the redistribution layer faces the first surface, a semiconductor chip between the substrate and the redistribution layer, the semiconductor chip spaced apart from the first surface and electrically connected to the third surface, a connection structure between the substrate and the redistribution layer and horizontally spaced apart from the semiconductor chip wherein the connection structure is electrically connected to the first surface and the third surface, and a dielectric layer between the substrate and the redistribution layer. The dielectric layer covers the semiconductor chip and the connection structure and extends between the semiconductor chip and the first surface.