Embedded Chip Package Structure for Signal Path Reduction
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Solution Overview
Problem
Conventional semiconductor package structures face challenges in miniaturization due to large signal transmission path lengths and signal losses caused by multiple media (solder bumps and tin balls) between the chip and packaging substrate, which cannot be reduced effectively.
Innovation Solution
A package structure with an embedded semiconductor chip and a carrier, where the chip is encapsulated with a dielectric layer and connected via conductive vias or solder material directly to a wiring layer, reducing the signal transmission path to a single medium and allowing for miniaturization by matching pitch with solder bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-chip package structure is used with solder bumps and tin balls, then electrical connection between chip and packaging substrate is achieved, but signal transmission path becomes too long and signal losses occur due to passing through different media
Solution Approach 1:
The patent merges the solder bump and tin ball connection layers into a single integrated wiring layer formed on the packaging substrate. This consolidation eliminates the intermediate tin ball layer, creating a direct electrical connection path from the chip's solder bumps to the substrate's wiring layer, thereby shortening the signal transmission path and reducing signal losses through multiple media interfaces.
Solution Approach 2:
The patent extracts and eliminates the tin ball intermediate connection layer from the conventional flip-chip structure. By removing this redundant connection layer and directly forming wiring patterns on the substrate that align with the chip's solder bumps, the signal transmission path is simplified and shortened, improving signal integrity.
2Volume of moving object
If conventional package structure is used, then chip mounting is achieved, but miniaturization requirement cannot be met due to large pitch of solder bumps
Solution Approach 1:
The patent transitions from a three-dimensional multi-layer connection structure (solder bumps through tin balls to substrate pads) to a two-dimensional planar wiring layer structure on the substrate. This dimensional simplification allows for more flexible layout design and smaller pitch configurations, enabling package miniaturization while maintaining manufacturing feasibility.
3Volume of moving object
If circuit of packaging substrate has small size, then miniaturization is achieved, but pitch of tin balls of chip cannot be reduced
Solution Approach 1:
Instead of reducing the chip's tin ball pitch to match the small substrate circuit size, the patent inverts the approach by forming the substrate's wiring layer to match the chip's existing solder bump pitch. This reversal allows the substrate to adapt to the chip's geometry, enabling miniaturization without compromising the chip's manufacturing specifications.
Data Source
AI summary
A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.