Embedded Chip Package Stacked Die Interconnect Warpage
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Solution Overview
Problem
Current embedded chip build-up processes face challenges such as high electrical resistance, inductance, and capacitance due to wire-bonding, leading to degraded device speed and increased power consumption, and struggle with 3D stacking and warpage issues, which hinder miniaturization and reliability in integrated circuit packaging.
Innovation Solution
The method involves using patterned laminate re-distribution layers with metal interconnects to create a direct metallic connection between chips and the input/output system, allowing for a stacked 3D arrangement of chips with reduced warpage and increased re-distribution layers without the need for stiffeners, by patterning and laminating polymer layers with vias and metal interconnects to form a lamination stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If wire-bonding is used to connect stacked chips, then chip stacking is achieved, but electrical resistance, inductance and capacitance increase causing degraded device speed and higher power consumption
Solution Approach 1:
The patent extracts and eliminates the wire-bonding interconnect layer from the stacked chip structure, replacing it with direct die-to-die bonding. This removes the intermediate wire bonds that contribute parasitic inductance, capacitance, and resistance, thereby improving electrical performance while maintaining 3D stacking capability
Solution Approach 2:
The patent transitions from planar wire-bonding connections to vertical direct-bonding connections through the use of through-silicon vias (TSVs) and direct die attachment. This dimensional change in interconnect architecture reduces the current path length and eliminates the need for lateral wire bonds, directly addressing the electrical performance degradation issue
2Adaptability or versatility
If eight or more re-distribution layers are applied in a layer-by-layer fashion, then routing capability is improved, but warpage occurs in the rerouting and interconnection system
Solution Approach 1:
The patent segments the re-distribution layers into multiple thin laminate layers rather than applying thick layers sequentially. Each thin layer contributes less to cumulative stress and warpage, while collectively providing the necessary routing capability through distributed signal paths across multiple layers
Solution Approach 2:
The patent changes the physical parameters of the laminate structure by using thin-film deposition techniques to create re-distribution layers with controlled thickness and material composition. This parameter optimization reduces the stress-induced warpage while maintaining electrical routing functionality
3Stability of the object's composition
If molded epoxy stress balance layer or metal stiffener is used to prevent warpage, then structural stability is improved, but device size increases
Solution Approach 1:
The patent extracts and eliminates the need for molded epoxy stress balance layers and metal stiffeners by fundamentally changing the lamination process. The improved process uses controlled thin-film deposition and optimized layer sequencing that inherently prevents warpage without requiring additional stiffening components, thereby reducing package size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical interconnect performance, reduces manufacturing cycle time, and minimizes warpage, enabling faster, more reliable, and smaller integrated circuit packages with improved device speed and lower power consumption.
Implementation Method 1
a plurality of metal interconnects electrically coupled to the I/O system and configured to electrically connect the first chip and the second chip to the I/O system, wherein each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with one of a metal interconnect on a neighboring re-distribution layer and a chip pad on the first or second chip
Implementation Method 2
a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack
Data Source
AI summary
An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.