Embedded Chip Packaging Assembly for Thin, Stable Imaging Modules

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Solution Overview

Problem

Existing semiconductor packaging structures hinder further miniaturization due to their design, which affects the overall size and stability of the packaging assembly.

Innovation Solution

A semiconductor packaging assembly that includes a circuit board with receiving holes for chips, a packaging body to secure the chips, and wires connecting the chips to welding pads, allowing for a compact and stable configuration with improved electrical connectivity and reduced stray light, facilitating miniaturization and enhanced imaging quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If conventional chip packaging structures (COB, Flip Chip, CSP) are used, then electrical connectivity is achieved, but the overall size and height of the packaging assembly cannot be further miniaturized

Engineering Contradiction:
Improvesize of packaging assemblyVSAvoidpackaging structure complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The chip is embedded within a receiving hole formed in the circuit board, creating a nested configuration where the chip sits inside the recessed cavity. This nesting approach allows the chip to be positioned below the surface level of the circuit board, reducing the overall height and volume of the packaging assembly while maintaining electrical connectivity through wires that route from the chip pins to surface mounting pads.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The invention transitions from conventional surface-level or top-mounted chip packaging to a three-dimensional configuration where the chip is positioned within a recessed cavity. By utilizing the vertical dimension (creating depth through the receiving hole), the packaging achieves compactness in the horizontal plane while managing vertical space efficiently, thereby reducing overall footprint without compromising electrical connection capabilities.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If chip is embedded in receiving hole, then size is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveheight of packaging assemblyVSAvoidmanufacturing process complexity
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The manufacturing process is divided into distinct sequential steps: first forming the receiving hole in the circuit board, then embedding the chip into this pre-formed cavity, and finally establishing wire connections from the embedded chip to surface pads. This segmentation of the manufacturing process into modular stages makes the complex task of creating an embedded chip structure more manageable and facilitates standardized production procedures.

Inventive Principle:
Principle #1Segmentation

3Reliability

If conventional packaging is used, then electrical connection is established, but stray light affects imaging quality

Engineering Contradiction:
Improveimaging qualityVSAvoidstray light
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The invention extracts or removes the harmful effect of stray light by utilizing the recessed receiving hole configuration. The cavity structure physically isolates the chip from the surface environment, creating a controlled optical environment that prevents stray light from reaching the chip's light-sensitive surfaces. This extraction of the harmful stray light factor from the system improves imaging quality while maintaining the electrical connection functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250015067A1Semiconductor packaging assembly and opto-electromechanical device having the same
Publication Date: 2025.01.09 RAYPRUS TECH (FOSHAN) CO LTD
  • US20250015067A1 patent drawing
  • US20250015067A1 patent drawing
  • US20250015067A1 patent drawing

AI summary

A semiconductor packaging assembly includes a circuit board, at least one chip, a packaging body, and wires. The circuit board includes a first surface, a second surface opposite to the first surface, at least one receiving hole recessed from the first surface, and first welding pads on the first surface. The chip is received in the receiving hole and spaced apart from the circuit board by a gap. Each chip includes an active surface opposite to the second surface, a passive surface opposite to the active surface, and pins on the active surface. The packaging body is received in the gap and bonded to the chip and the circuit board. The wires are attached to a third surface of the packaging body opposite to the second surface and each wire is electrically connected to at least one of the pins and at least one of the first welding pads.