Embedded Wafer-Level Chip Packaging for Low-Damage Die Singulation
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in efficiently processing semiconductor wafers and dies of varying sizes, leading to equipment obsolescence and increased capital investment due to the need for specialized equipment for each size, and the semiconductor dies are prone to damage during singulation and exposure.
Innovation Solution
The use of a standardized carrier that can accommodate semiconductor dies of various sizes, allowing for flexible manufacturing by singulating wafers into a reconstituted wafer level chip scale package (eWLCSP) using a common set of processing tools, reducing the need for specialized equipment and minimizing die damage during handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional specialized equipment is used for each semiconductor die size, then processing precision is maintained, but device complexity and capital investment increase
Solution Approach 1:
The patent implements a universal carrier system that can accommodate semiconductor dies of various sizes using a single carrier design. The carrier includes a standardized mounting surface and positioning features that adapt to different die dimensions, eliminating the need for multiple specialized carriers and processing equipment for each die size while maintaining manufacturing precision through standardized positioning mechanisms.
Solution Approach 2:
The patent segments the carrier system into standardized modular components, including a base carrier structure and interchangeable positioning elements. This segmentation allows the same carrier platform to be configured for different die sizes by adjusting positioning features, reducing equipment complexity while preserving processing precision through consistent modular interfaces.
2Manufacturing precision
If specialized equipment is used for each semiconductor die size, then processing accuracy is improved, but loss of time and productivity decrease
Solution Approach 1:
The universal carrier system enables a single processing line to handle multiple die sizes without requiring equipment changes or reconfiguration. The standardized carrier design allows continuous processing of different die sizes on the same equipment, eliminating downtime associated with equipment swaps and maintaining processing accuracy through consistent positioning features across all carrier configurations.
Solution Approach 2:
The carrier system incorporates dynamic positioning features that can be adjusted to accommodate different die sizes while maintaining precise alignment. This dynamic adaptability allows the same equipment to process various die sizes with consistent accuracy, improving productivity by eliminating the need for dedicated equipment for each die size while preserving processing accuracy through adjustable positioning mechanisms.
3Manufacturing precision
If semiconductor dies are handled individually during singulation, then manufacturing precision is maintained, but damage risk increases
Solution Approach 1:
The patent merges multiple semiconductor dies onto a single carrier during the singulation process, allowing them to be handled and processed collectively rather than individually. This combined handling approach maintains singulation precision through the carrier's standardized positioning features while reducing damage risk by minimizing the number of times individual dies are picked up and manipulated during the manufacturing process.
Solution Approach 2:
The carrier system performs preliminary positioning and support of semiconductor dies before final singulation and packaging. By establishing precise positioning and providing mechanical support early in the process, the system maintains singulation precision while protecting dies from damage during subsequent handling operations through the carrier's protective structure.
Data Source
AI summary
A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.