Embedded Chip Substrate Eliminating Dam for Compact Design
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Solution Overview
Problem
Conventional packaging substrates with photosensitive semiconductor chips face challenges in miniaturization due to increased area and height requirements, warping issues, and complex fabrication processes, which are not optimal for compact-sized electronics products.
Innovation Solution
A packaging substrate with an embedded semiconductor chip is fabricated using a core board with a through cavity, dielectric layers, and conductive through holes, eliminating the need for a dam and wires, allowing for a compact design with reduced structural height and area by forming a light-permeable window and using adhesive and solder mask layers for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dam is formed around the semiconductor chip to seal it, then the chip is protected and a level plane is provided, but the processing difficulty increases and the overall height of the package structure increases
Solution Approach 1:
The patent removes the dam structure from the package design, extracting the sealing function to the light-permeable layer instead. This eliminates the complex multi-step dam formation process (drilling, plating, forming) while maintaining chip protection through the adhesive-sealed cavity approach.
2Stability of the object's composition
If the core board is made thicker to prevent warping and maintain parallel alignment, then stability is improved, but the overall size of the packaging substrate increases
Solution Approach 1:
The patent addresses warping prevention not by increasing thickness in the vertical dimension, but by redistributing structural support through the adhesive layer and light-permeable layer in the horizontal plane. The adhesive secures the chip to the board, providing mechanical stability without requiring excessive board thickness.
3Reliability
If space is reserved on the core board to form the dam, then the chip is properly sealed, but the overall layout area of the packaging substrate increases
Solution Approach 1:
The patent merges the sealing function with the light-permeable layer, which serves dual purposes: protecting the chip cavity and allowing light transmission. This eliminates the need for a separate dam structure and its associated layout space, as the light-permeable layer extends over the chip area without requiring additional peripheral space.
4Reliability
If the height of the dam is increased to accommodate conducting wires, then electrical connections are maintained, but the overall height of the package structure increases
Solution Approach 1:
The patent removes the dam structure that forced wire routing above the chip surface. Instead, wires can be routed on the board plane level, eliminating the need for vertical clearance above the chip and reducing overall package height while maintaining electrical connection stability through standard PCB trace routing.
Data Source
AI summary
A packaging substrate having a semiconductor chip embedded and a fabrication method thereof are provided. The method includes forming a semiconductor chip in a through cavity of a core board and exposing a photosensitive portion of the semiconductor chip from the through cavity; sequentially forming a first dielectric layer and a first circuit layer on the core board, the first circuit layer being electrically connected to the electrode pads of the semiconductor chip; forming a light-permeable window on the first dielectric layer to expose the photosensitive portion of the semiconductor chip and adhering a light-permeable layer onto the light-permeable window, thereby permitting light to penetrate through the light-permeable layer to reach the photosensitive portion. Therefore, when fabricated with the method, the packaging substrate dispenses with conductive wires and dams and thus can be downsized.