Embedded Chip Substrate with Metallic Board Heat Dissipation
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Solution Overview
Problem
Current flip-chip semiconductor packaging technologies face issues with high fabrication costs due to the use of Sn—Pb materials, thermal stress mismatch between semiconductor chips and organic circuit boards, and ineffective heat dissipation, leading to reliability problems and environmental concerns.
Innovation Solution
A semiconductor package substrate with a metallic board, insulating layers, and a support plate is fabricated, where the semiconductor chip is mounted on the metallic board with a support plate having a through cavity, and insulating materials fill the gap between the chip and the support plate, providing heat dissipation and electromagnetic shielding, while copper circuits are used for electrical connections, eliminating the need for Sn—Pb materials and reducing fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps or conductive adhesive materials are used for electrical connection between chip and circuit board, then electrical connection is achieved, but fabrication cost increases and environmental problems arise due to Sn-Pb materials
Solution Approach 1:
The patent removes the underfill encapsulation step from the conventional packaging process. By designing a package structure where the support plate directly contacts the circuit board and the chip is mounted on the support plate, the patent eliminates the need for underfill resin, thereby reducing fabrication steps and costs while avoiding environmental concerns associated with Sn-Pb materials
Solution Approach 2:
The patent divides the package structure into distinct functional layers: the support plate serves as both a mechanical support and a heat dissipation component, while the circuit board provides electrical connection. This segmentation allows each component to perform its specific function optimally without requiring additional encapsulation materials
2Reliability
If underfill resin is used to fill gap between chip and circuit board, then thermal expansion mismatch is reduced, but fabrication steps increase and quality stability deteriorates due to flash problems
Solution Approach 1:
The patent extracts the underfill encapsulation function from the package structure. By designing the support plate with appropriate thermal expansion properties and ensuring direct contact between the support plate and circuit board, the patent achieves thermal stress resistance without requiring underfill resin, thereby eliminating the associated fabrication complexity and quality issues
Solution Approach 2:
The patent applies local quality by selecting materials with specific thermal expansion coefficients for the support plate and circuit board. The support plate is designed to have thermal expansion properties that match both the chip and the circuit board, creating a gradual transition that reduces thermal stress without requiring additional encapsulation materials
3Reliability
If conventional flip-chip packaging is used with lengthy metallic wires, then electrical connection is achieved, but electrical performance is limited due to lengthy connection paths
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical stacking. The chip is mounted face-down on the support plate with electrode pads facing the circuit board, creating direct vertical electrical pathways that eliminate lengthy lateral connection paths and improve signal speed
4Device complexity
If heat dissipation is not effectively addressed in semiconductor packages, then packaging simplicity is maintained, but chip performance and lifetime are severely affected
Solution Approach 1:
The support plate is designed to perform multiple functions simultaneously: it provides mechanical support for the chip, serves as a heat dissipation pathway through its thermal conductivity, and enables electrical connection between the chip and circuit board. This multi-functionality eliminates the need for separate heat sink components while improving chip reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies fabrication processes, enhances reliability by preventing flashes and voids, improves heat dissipation and electrical performance, and reduces material costs and environmental impact by using copper circuits and minimizing the use of Sn—Pb materials.
Implementation Method 1
the semiconductor chip is mounted on the metallic board with a support plate having a through cavity, and insulating materials fill the gap between the chip and the support plate, providing heat dissipation
Implementation Method 2
the semiconductor chip is mounted on the metallic board with a support plate having a through cavity, and insulating materials fill the gap between the chip and the support plate, providing heat dissipation and electromagnetic shielding
Implementation Method 3
copper circuits are used for electrical connections, eliminating the need for Sn—Pb materials
Data Source
AI summary
A semiconductor package substrate with embedded chip and a fabrication method thereof are provided. A first insulating layer is applied on a metallic board, and formed with at least one opening for exposing a portion of the metallic board. At least one semiconductor chip is mounted on the exposed portion of the metallic board. A support plate is mounted on the first insulating layer, and formed with a through cavity at a position corresponding to the opening of the first insulating layer, for receiving the chip in the through cavity. A second insulating layer is applied on the chip and the support plate. Insulating materials of the insulating layers fill a gap between the chip and the support plate. A circuit layer is formed on the second insulating layer, wherein the circuit layer is electrically connected to the chip by conductive structures formed in the second insulating layer.