Embedded-Chip Package Substrate With Integrated Underfill Bonding
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Solution Overview
Problem
The flip-chip bonding method in semiconductor packaging faces challenges with weakened adhesion reliability between bumps and pads, requiring a separate underfill process that increases manufacturing time and substrate size.
Innovation Solution
A package substrate design that forms an underfill surrounding the chip using an insulating layer, eliminating the need for a separate underfill process by softening and shaping the insulating layer during chip mounting, and utilizing a multilayer structure with different material properties to enhance bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate underfill process is used to improve adhesion reliability between bumps and pads, then bonding strength is improved, but manufacturing time and process complexity increase
Solution Approach 1:
The patent combines the underfill function with the insulating layer by making the insulating layer extend beyond the chip mounting area to form an underfill portion. This integration eliminates the need for a separate underfill application and curing process, reducing manufacturing steps and time while maintaining the adhesion reinforcement function.
Solution Approach 2:
The insulating layer is designed to serve multiple functions: electrical insulation, mechanical support, and adhesion reinforcement (underfill function). By making the insulating layer extend beyond the chip area, it simultaneously performs insulation and provides the underfill effect that improves bump-pad adhesion reliability.
2Reliability
If a separate underfill process is used to improve adhesion reliability, then bonding strength is improved, but device complexity increases
Solution Approach 1:
The patent merges the underfill process with the insulating layer formation process. The insulating layer is applied in a single step that covers both the chip mounting area and the extended area that will serve as underfill, eliminating the need for separate underfill application and curing processes.
Solution Approach 2:
The insulating layer is designed to perform multiple functions including electrical insulation, mechanical support, and adhesion reinforcement. This multi-functionality reduces the number of separate processes needed, thereby simplifying the overall manufacturing process while maintaining improved adhesion reliability.
3Reliability
If substrate size is increased to secure space for underfill formation, then underfill can be properly formed, but substrate area increases
Solution Approach 1:
The patent combines the underfill space with the insulating layer area. The insulating layer extends beyond the chip mounting area to provide the underfill portion, eliminating the need for additional substrate area dedicated solely to underfill formation. The same insulating layer material and space serve dual purposes.
4Reliability
If substrate thickness is increased to accommodate separate underfill layer, then underfill can be formed, but package substrate size increases
Solution Approach 1:
The patent integrates the underfill function into the insulating layer, eliminating the need for a separate underfill layer. The insulating layer extends beyond the chip area to form an underfill portion, so no additional thickness is required beyond what is already needed for the insulating layer itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces substrate thickness, and improves bonding reliability by forming an underfill naturally during chip mounting, enhancing the overall strength and reducing the size of the package substrate.
Implementation Method 1
softening and shaping the insulating layer during chip mounting
Data Source
AI summary
A package substrate according to an embodiment includes a first substrate; and a first chip mounted on the first substrate; wherein the first substrate includes: a first insulating layer including a first region overlapping the first chip in a vertical direction and a second region other than the first region; and a circuit pattern disposed on the first region and the second region of the first insulating layer; wherein the circuit pattern includes: a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion buried in the first region of the first insulating layer, and a third portion including at least a part buried in the first region of the first insulating layer and connecting between the first portion and the second portion; wherein at least a part of the first chip is disposed in the first region of the first insulating layer; wherein the first region of the first insulating layer surrounds a lower surface and a side surface of the first chip, and wherein the first region and the second region of the first insulating layer are a single insulating layer.