Embedded Chip Packaging Structure With Via-Pillar Heat Dissipation
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Solution Overview
Problem
Current electronic device packaging structures face challenges with heat dissipation efficiency due to limited heat dissipation areas and warping issues in substrates, where the thermal conductivity of thermal contact layer materials is significantly lower than metal layers, and the thick copper layer coverage is inadequate, leading to reliability problems and manufacturing difficulties.
Innovation Solution
A circuit prearranged heat dissipation embedded packaging structure is introduced, featuring a support frame with a via pillar and wiring layers that connect the heat dissipation layer to the chip, increasing the heat dissipation area and efficiency while reducing substrate warping and manufacturing complexities, and addressing glass fiber exposure issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thick copper layer is formed on the back face of the chip for heat dissipation, then heat dissipation efficiency is improved, but the copper layer can only be arranged on the back face of the chip so that the heat dissipation area is limited
Solution Approach 1:
The patent extends heat dissipation from a single surface (back face of chip) to multiple surfaces by adding a first wiring layer on the lower surface of the support frame and a second wiring layer on the upper surface of the support frame. This multi-dimensional arrangement increases the total heat dissipation area while maintaining efficient thermal conduction pathways.
Solution Approach 2:
The heat dissipation function is segmented across multiple components: the thick copper layer on the chip back face, the first wiring layer on the support frame lower surface, and the second wiring layer on the support frame upper surface. Each segment contributes to overall heat dissipation, distributing the thermal management function across the structure.
2Temperature
If a thick copper layer is formed on the back face of the chip, then heat dissipation is facilitated, but other areas of the substrate are not covered by thick copper so that the problem of warping of local areas of the substrate is easily caused
Solution Approach 1:
The patent merges the heat dissipation function with the structural support function by integrating thick copper wiring layers into the support frame structure. The first and second wiring layers are formed as integral parts of the support frame, combining mechanical support and thermal management in a single unified structure that prevents warping while facilitating heat dissipation.
Solution Approach 2:
The support frame is designed with multi-functionality, serving both as a mechanical support structure and as a heat dissipation pathway. The first and second wiring layers on the support frame perform dual functions of structural reinforcement and thermal conduction, eliminating the need for separate heat dissipation components that could cause warping.
3Temperature
If the copper layer is arranged only on the back face of the chip, then heat dissipation is achieved, but the rewiring process of the embedded chip is increased and the yield of the embedded substrate is reduced
Solution Approach 1:
The first wiring layer is pre-formed on the lower surface of the support frame before the chip is mounted. This preliminary action allows thermal conduction pathways to be established in advance, eliminating the need for complex post-chip-mounting rewiring processes and improving manufacturing yield.
Solution Approach 2:
The support frame acts as an intermediary structure that provides pre-established thermal conduction pathways between the chip and the external environment. The first and second wiring layers on the support frame serve as intermediate heat transmission channels, simplifying the overall thermal management architecture and reducing manufacturing complexity.
4Area of stationary object
If storey-addition of the back thick copper layer is performed, then heat dissipation area is increased, but the copper surface needs to be exposed through a copper pillar method so that the thickness of the storey-addition dielectric layer is difficult to control
Solution Approach 1:
Instead of vertically stacking copper layers (storey-addition) which complicates dielectric layer thickness control, the patent distributes copper wiring layers across different horizontal surfaces: the lower surface of the support frame (first wiring layer) and the upper surface of the support frame (second wiring layer). This horizontal distribution maintains increased heat dissipation area while avoiding the manufacturing precision issues of vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances heat dissipation efficiency, reduces substrate warping and manufacturing defects, and improves yield by dispersing heat through additional wiring layers and via pillars, ensuring reliable heat management and reduced risk of plate folding.
Implementation Method 1
a heat dissipation layer on the back face of the chip... the first wiring layer is in conductive connection with the heat dissipation layer
Implementation Method 2
a via pillar passing through the support frame... the second wiring layer is in conductive connection with the first wiring layer through the via pillar
Data Source
AI summary
A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.