Embedded Chiplet Metallization for Dense IC Interconnects
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Solution Overview
Problem
Current IC integration techniques face limitations such as high cost, low insertion efficiency, and increased z-height due to latency and energy inefficiencies in packaging and interconnect density, particularly in multi-chip packages and wafer-level stacking methods.
Innovation Solution
The integration of an IC chiplet within the back-end metallization layers of a host IC chip using hybrid monolithic and die-level bonding techniques, allowing for higher density interconnects and flexible alignment, which enhances interconnect density and reduces z-height by embedding chiplets at lower metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip package (MCP) techniques are used to integrate multiple IC chips, then flexibility in combining heterogeneous silicon processes is improved, but interconnect density and energy efficiency deteriorate due to package routing limitations
Solution Approach 1:
The patent embeds a chiplet within the metallization layers of a host IC chip, nesting one functional unit inside another. This allows the chiplet to be integrated directly into the host chip's interconnect structure, achieving high interconnect density while maintaining flexibility in combining different silicon processes. The chiplet is surrounded by and electrically connected to the host chip's metallization layers, creating a nested configuration that resolves the contradiction between versatility and interconnect density.
2Quantity of substance
If wafer-level stacking is used to increase electrical connections, then connection density is improved, but manufacturing complexity and cost increase due to requiring substantially the same die size and compounded yield loss
Solution Approach 1:
The patent divides the integrated circuit system into separate functional units: a host IC chip and a smaller chiplet. This segmentation allows the chiplet to be fabricated using a different silicon process and size than the host chip, eliminating the requirement for matched die sizes. The chiplet can be independently tested and selected, reducing compounded yield loss while maintaining high electrical connection density through direct integration into the host chip's metallization layers.
3Adaptability or versatility
If die stacking is performed after metallization layers are completed, then flexibility in die selection is improved, but interconnect density deteriorates due to limited support for fine pitches in thick metallization layers
Solution Approach 1:
The patent performs preliminary actions by embedding the chiplet within the metallization layers of the host IC chip during the fabrication process, rather than stacking completed dies afterward. This allows the chiplet to be integrated at an intermediate stage when the metallization layers are still being formed, enabling fine-pitch interconnects to be created simultaneously with the host chip's metallization. This preliminary integration maintains flexibility in die selection while achieving high interconnect density.
4Length of stationary object
If chiplets are embedded at lower metallization layers, then z-height is reduced, but manufacturing precision requirements increase for alignment and integration
Solution Approach 1:
The patent merges the chiplet integration process with the host IC chip's metallization fabrication process. By combining these operations, the chiplet alignment and metallization formation are performed simultaneously, reducing the cumulative alignment errors that would occur with sequential processes. This merging of operations enables embedding at lower metallization layers (reducing z-height) while maintaining achievable manufacturing precision through coordinated process control.
Data Source
AI summary
Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.