Embedded Semiconductor Chips in Laminate Substrates
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing integration, electrical performance, and thermal efficiency, particularly in multi-chip configurations, where existing designs often compromise on size, complexity, and operational performance.
Innovation Solution
The semiconductor devices incorporate a laminate structure with embedded and surface-mounted semiconductor chips, utilizing redistribution layers and encapsulation materials to create a compact, high-pin-count configuration that supports advanced electrical connections and thermal management, enabling increased integration and improved performance in applications like DC/DC converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a multi-chip configuration, then the degree of integration and functionality are improved, but the device size and structural complexity increase
Solution Approach 1:
The patent divides the semiconductor device into multiple independent semiconductor chips, each performing specific functions (power semiconductor chip for switching, control semiconductor chip for control logic). These segmented chips are mounted on a common substrate, allowing functional integration while maintaining manufacturing simplicity and design flexibility for each chip module
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by mounting multiple semiconductor chips vertically on a common substrate. This vertical arrangement increases integration density and functionality without proportionally increasing the horizontal device footprint, effectively resolving the contradiction between integration degree and device size
2Reliability
If multiple semiconductor chips are integrated to increase functionality, then electrical performance is improved, but parasitic inductances and capacitances increase
Solution Approach 1:
The patent introduces a common substrate as an intermediary platform that provides optimized electrical interconnection between multiple semiconductor chips. The substrate includes specifically designed conductive patterns and via structures that minimize parasitic inductances and capacitances in the inter-chip connections, thereby maintaining high electrical performance while enabling multi-chip integration
Solution Approach 2:
The patent optimizes electrical parameters by carefully designing the conductive trace widths, via dimensions, and material selections in the substrate interconnections. By adjusting these geometric and material parameters, the substrate minimizes parasitic effects while maintaining signal integrity and power delivery across the multi-chip device
3Volume of moving object
If device size is reduced for compactness, then integration density is improved, but thermal management becomes more difficult
Solution Approach 1:
The patent merges multiple semiconductor chips and their interconnections onto a single common substrate, creating a compact integrated assembly. This consolidation reduces the overall device volume while maintaining effective thermal pathways through the substrate, as the close proximity of chips to the substrate enables efficient heat conduction away from active regions
Data Source
AI summary
A semiconductor device includes a laminate, a first semiconductor chip at least partly embedded in the laminate, a second semiconductor chip mounted on a first main surface of the laminate, and a first electrical contact arranged on the first main surface of the laminate. The second semiconductor chip is electrically coupled to the first electrical contact.