Embedded Chipset PCB Layout for Thin High-Integration Boards
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Solution Overview
Problem
Existing circuit boards face challenges in achieving ultra-thinness, miniaturization, high integration, low power consumption, and low cost while meeting demands for performance, reliability, and heat dissipation, with current technologies not well integrated in the manufacturing process.
Innovation Solution
A circuit board design featuring a core board with slots for first and second sub-slots, where first and second chips are connected in series to form chipsets, which are then connected in parallel with power and ground layers, and insulated by multiple layers to reduce signal loss and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If chips are embedded within a core layer and connected to power and signal layers on either side, then the circuit board can be made thinner, but the manufacturing process becomes more complex
Solution Approach 1:
The patent embeds chips within the core layer and nests multiple functional layers (power signal layers, ground layers, insulating layers) around the chips in a compact stacked configuration. This nesting approach allows the circuit board to achieve ultra-thinness by integrating multiple functions within a compact vertical structure, while the standardized embedding process helps manage manufacturing complexity
Solution Approach 2:
The patent transitions from planar circuit board design to a three-dimensional stacked architecture where chips are embedded within the core layer and connected to power and signal layers on either side. This dimensional change enables significant thickness reduction while maintaining functionality, and the systematic layer stacking provides a manageable manufacturing approach
2Adaptability or versatility
If multiple chips are embedded and connected in series to form chipsets, then integration is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple chips by connecting them in series to form integrated chipsets within the core layer. Power signal layers and ground layers are also merged and positioned on either side of the core layer to provide unified power distribution and grounding for all chipsets. This merging approach achieves high integration while the standardized layer configuration helps control structural complexity
Solution Approach 2:
The patent creates universal power signal layers and ground layers that serve multiple chipsets simultaneously. These layers provide common power distribution and grounding functions across the entire circuit board, enabling high integration of multiple chipsets while reducing the need for separate dedicated layers for each chip, thus managing structural complexity
3Reliability
If power signal layers and ground layers are placed on both sides of the core layer, then signal transmission quality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes both sides of the core layer to position power signal layers and ground layers in a symmetric stacked configuration. This three-dimensional arrangement provides excellent signal reference planes and reduces electromagnetic interference, improving signal transmission quality. The symmetric structure on both sides provides manufacturing repeatability that helps offset the increased process complexity
Solution Approach 2:
The patent positions ground layers adjacent to power signal layers on both sides of the core layer to create equipotential reference planes. This configuration provides stable reference potentials for signal transmission, reducing noise and improving signal quality. The standardized equipotential layer arrangement facilitates consistent manufacturing processes
Data Source
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AI summary
The circuit board provided by the present disclosure including: a core board, defining a plurality of slots, the plurality of slots including a plurality of first sub-slots and a plurality of second sub-slots disposed beneath the plurality of first sub-slots; wherein each of the second sub-slots is located beneath a corresponding first sub-slot of the plurality of first sub-slots; and a plurality of chip assemblies, arranged in the plurality of slots and including a plurality of first chips located in the plurality of first sub-slots and a plurality of second chips located in the plurality of second sub-slots. Each of the plurality of first chips is connected in series with one of the plurality of second chips at a corresponding position to form a plurality of chipsets; the plurality of chipsets are connected in parallel with each other; an end of the plurality of chipsets is connected to a first power signal layer, and the other end of the plurality of chipsets is connected to a ground layer. In this way, the chip is embedded in the circuit board and the circuit board combined to achieve the thinness and miniaturization of the circuit board.