Embedded Circuit Design Using 2D Cross-Sectional Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional approaches for analyzing electronic designs with embedded circuits require excessive computational resources and memory, leading to long processing times and significant delays in design cycles due to the need for detailed 3D modeling and large s-parameter calculations.
Innovation Solution
The method involves transforming the electronic design by adding artificial layers and metal patches to re-establish connectivity, allowing for the generation of a transformed model that can be analyzed using hybrid solvers to predict electromagnetic behaviors without the need for extensive 3D modeling, thereby reducing memory usage and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional 3D modeling and solving approaches are used to analyze electronic designs with embedded circuits, then accurate electromagnetic field analysis is achieved, but processor runtime increases by nearly ten times and memory usage increases by 15%
Solution Approach 1:
The patent segments the electronic design into distinct layers (conductor layers, dielectric layers) and processes each layer separately using 2.5D solvers rather than treating the entire structure as a 3D model. This segmentation allows the complex 3D electromagnetic problem to be divided into manageable 2D cross-sectional problems, dramatically reducing computational complexity and processing time while maintaining accuracy for planar structures.
Solution Approach 2:
The patent creates 2D cross-sectional copies of the 3D electromagnetic structure at different heights through the dielectric layers. These 2D copies represent the electromagnetic field distribution at each layer interface, allowing analysis without requiring full 3D modeling. This copying approach preserves the essential electromagnetic characteristics while avoiding the computational burden of complete 3D simulation.
2Measurement precision
If detailed 3D modeling is performed for embedded circuits between layers, then accurate electrical characteristic determination is achieved, but memory footprint becomes prohibitively large
Solution Approach 1:
The patent divides the three-dimensional electromagnetic structure into two-dimensional cross-sections at each conductor layer interface. Instead of storing and processing the entire 3D model in memory, the system processes each 2D slice independently, significantly reducing the memory requirements while capturing the essential electromagnetic behavior of the layered structure.
Solution Approach 2:
The patent transforms the 3D electromagnetic analysis problem into a series of 2D analysis problems by examining cross-sections at different heights. This dimensionality reduction from 3D to 2D allows the system to analyze complex multi-layer structures with embedded circuits using significantly less memory, as 2D solvers require far fewer computational resources than their 3D counterparts.
3Reliability
If conventional two-step approaches with iterative solving are used, then electrical characteristics are determined, but design cycle time increases due to computational bottlenecks
Solution Approach 1:
The patent segments the iterative analysis process into independent 2D cross-sectional analyses that can be performed simultaneously or in sequence without requiring repeated full 3D simulations. Each 2D slice provides localized electromagnetic characteristics that contribute to the overall design validation, eliminating the computational bottleneck of conventional iterative 3D solving while maintaining characterization accuracy.
Solution Approach 2:
The patent applies 2D cross-sectional analysis to the essential critical paths and signal routes within the embedded circuit structure, performing analysis only where needed rather than exhaustive full 3D modeling throughout. This partial action approach achieves sufficient accuracy for design validation while dramatically reducing the computational burden and accelerating the design cycle.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.