Embedded Circuit Board Blind Via Thickness Control
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Solution Overview
Problem
The existing manufacturing processes for embedded circuit boards face challenges in achieving uniform thickness of conductive layers due to differences in blind via and intaglio pattern depths, leading to non-uniform electroplating, residual material issues, and reduced manufacturing yield and reliability.
Innovation Solution
A circuit board design featuring a circuit substrate with a dielectric layer, blind vias, and intaglio patterns, where a first conductive layer is formed within the intaglio patterns and blind vias, and a barrier layer is used to control the etching process, allowing for the formation of second and third circuits with different conductive layers, ensuring precise thickness control and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electroplating process is performed to form conductive layer in blind via and intaglio pattern, then conductive layer is formed, but thickness of conductive layer becomes non-uniform due to different depths of blind via and intaglio pattern
Solution Approach 1:
A filling layer is formed to fill the blind via before the electroplating process. This preliminary action equalizes the depth between the blind via and intaglio pattern, ensuring uniform electroplating thickness. The filling layer acts as a placeholder that brings the surface levels to match, allowing subsequent electroplating to proceed uniformly across both structures.
Solution Approach 2:
The patent changes the physical state of the blind via from an empty cavity to a filled structure by introducing the filling layer. This parameter change (from void to solid material) equalizes the depth parameter between blind via and intaglio pattern, enabling uniform electroplating thickness control.
2Manufacturing precision
If conductive layer is removed after electroplating, then external conductive material is removed, but it is difficult to control the thickness of removed conductive layer and residual conductive material is left on dielectric layer
Solution Approach 1:
The filling layer serves as an intermediary structure that facilitates controlled removal. By having the filling layer in place during electroplating, it creates a uniform baseline that allows precise control over how much conductive layer is removed subsequently, preventing residual material issues.
3Productivity
If build-up circuit layer is formed on dielectric layer, then circuit structure is built up, but electroplating process produces undesirable quality and low yield
Solution Approach 1:
The filling layer is formed as a preliminary action before the electroplating process that creates build-up circuit layers. This preliminary equalization of depths ensures that subsequent electroplating for build-up layers proceeds uniformly, improving both yield and quality by preventing the depth-related defects that cause rework and failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing yield and reliability of embedded circuit boards by allowing for precise control of conductive layer thickness and minimizing residual material issues, resulting in improved circuit board quality.
Implementation Method 1
A surface of the dielectric layer is irradiated by a laser beam to form an intaglio pattern and a blind via connecting the circuit layer
Implementation Method 2
An electroplating process is performed to form a conductive layer filling the blind via and the intaglio pattern
Data Source
AI summary
A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer.


