Embedded Circuit Package With Laminate Cavities
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Solution Overview
Problem
Current methods for vertical integration in semiconductor packaging, such as flip chip and face-up technologies, face challenges with complexity, cost, and limitations in accommodating lateral components due to requirements for redistribution layers and alignment accuracy, while wire bonding is hindered by laminate-induced pressure.
Innovation Solution
The method involves using laminates with cut-outs to form cavities for wire bonding in a 3D structure, eliminating the need for an upper connection layer and allowing additional stacks, using fibrous or thermoplastic support layers, and enabling the integration of various components like dies, resistors, and capacitors with aluminum wire for higher temperature applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used to connect components to the substrate, then ease of manufacture and adaptability improve, but laminate pressure squash the wire connections causing reliability issues
Solution Approach 1:
The laminate structure is segmented by introducing cavities that create localized void spaces. These cavities segment the continuous laminate pressure, allowing wire bonds to exist in protected zones where they are not subjected to compressive forces from the laminate layers.
Solution Approach 2:
The cavities act as intermediary spaces between the wire bonds and the laminate structure. By introducing this intermediate void zone, the wire bonds are shielded from the detrimental effects of laminate pressure while maintaining the structural integrity of the overall package.
2Productivity
If flip chip or face up technologies are used for vertical integration, then packing density improves, but device complexity and manufacturing cost increase due to redistribution layers and alignment requirements
Solution Approach 1:
The invention extracts and removes the complex redistribution layer requirement from the vertical integration process. By using wire bonding instead of flip chip or face-up technologies, the need for additional patterned connection layers is eliminated, simplifying the overall device structure while maintaining high packing density.
Solution Approach 2:
Instead of using planar connection methods (flip chip or face-up with redistribution layers) to achieve vertical integration, the invention inverts the approach by using wire bonding that extends vertically through cavities in the laminate, achieving three-dimensional integration without the complexity of traditional methods.
3Reliability
If an upper patterned connection layer is added to support wire bonding, then connectivity improves, but manufacturing cost and logistics complexity increase due to additional PCB processing steps
Solution Approach 1:
The invention merges the support function with the existing laminate structure by creating cavities within the laminate itself. This eliminates the need for a separate upper patterned connection layer, as the laminate with integrated cavities provides both structural support and the necessary connection pathways through the wire bonds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the packaging process by reducing costs and complexity, enabling the integration of multiple components in a vertically stacked package with enhanced flexibility and temperature tolerance, while allowing for the inclusion of additional components and conductor pathways.
Implementation Method 1
wire bonding the one or more components to the bond pads of the patterned conductor layer with bonding wires
Implementation Method 2
laminating a first series of support layers, each with one or more cut-outs
Data Source
AI summary
An embedded integrated circuit package is made by providing a substrate with a patterned conductor layer defining bond pads. One or more components typically with upwardly facing contact pads are mounted on the substrate. The contact pads are wire bonded to the bond pads of the patterned conductor layer. A series of layers, each with one or more cut-outs corresponding to locations of the components forms a first solid stack containing cavities accommodating the components and associated wires. In one embodiment the layers are fiberglass layers and the layers are cured in the presence of a resin to form a solid body. In another embodiment the layers are thermoplastic layers.