Embedded-Clock Serial Data Links for High-Speed ADC Output
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Solution Overview
Problem
High-speed analog to digital converter (ADC) systems face challenges in complex routing and high power requirements due to numerous pins in parallel transmission, while serial transmission is complex and inefficient with skewing issues and inadequate error checking.
Innovation Solution
A high-speed transmission system that uses an embedded clock, eliminating the need for separate clock pins, and incorporates a marker word with error checking and correction for robust real-time error detection and correction, allowing for efficient data packet assembly and serialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parallel transmission is used, then implementation simplicity is improved, but the number of interconnect lines increases requiring more space and complex routing
Solution Approach 1:
The parallel data bus is segmented into multiple serial channels, each transmitting a portion of the data bits. This segmentation reduces the number of interconnect lines required while maintaining the overall data transmission capability through parallel processing of multiple serial streams
Solution Approach 2:
The patent transitions from a single-plane parallel transmission to a multi-dimensional approach by organizing data into multiple serial channels with embedded clock signals. This dimensional reorganization allows efficient use of interconnect lines while maintaining high-speed data transfer
2Ease of manufacture
If parallel transmission is used, then implementation simplicity is improved, but power consumption increases due to more output drivers
Solution Approach 1:
The power consumption is reduced by segmenting the single high-power parallel output into multiple lower-power serial outputs. Each serial channel requires fewer output drivers operating at lower power levels, while the aggregate transmission capability is maintained through multiple channels
Solution Approach 2:
The patent redistributes the power load across multiple serial channels with embedded clocking, eliminating the need for separate high-power clock drivers. This dimensional transformation of the transmission architecture reduces overall power consumption while maintaining data integrity
3Device complexity
If serial transmission is used, then the number of data lines is reduced, but data rate per line must be much higher and implementation becomes more complex
Solution Approach 1:
The patent merges the clock signal and data transmission into a single serial channel by embedding the clock within the data stream. This combination eliminates the need for separate high-speed clock lines while maintaining synchronized data transfer at reduced speeds
Solution Approach 2:
The patent uses multiple serial channels with embedded clocking to distribute the data rate requirement across several lower-speed lines. This dimensional approach allows the system to achieve high overall throughput without requiring any single line to operate at extremely high speeds
4Ease of operation
If separate clock pin is used, then clock alignment is simplified, but the number of pins increases and routing becomes more complex
Solution Approach 1:
The patent merges the clock function into the data transmission channel by embedding clock signals within the serialized data stream. This integration eliminates separate clock pins while maintaining reliable clock alignment through the embedded timing information
Solution Approach 2:
The serial data line serves multiple functions simultaneously: it transmits both data and clock information. This multi-functionality reduces the total pin count while maintaining the ability to perform synchronized data transfer without separate dedicated clock lines
5Device complexity
If JEDEC JESD204 encoding is used, then clock pin is eliminated, but efficiency is limited to maximum 80% due to 8B/10B encoding overhead
Solution Approach 1:
The patent changes the encoding parameters by using a more efficient encoding scheme than traditional 8B/10B. The custom encoding achieves higher density by optimizing the balance between electrical balance maintenance and data transmission efficiency, resulting in greater than 87% efficiency
Solution Approach 2:
The patent creates a customized encoding approach that copies the essential features of 8B/10B (electrical balance and error detection) while eliminating the excessive overhead. This selective copying and optimization achieves better efficiency while maintaining the benefits of clock elimination
Data Source
Figure 1A~1C
Figure 2
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AI summary
A high speed transmission system includes at least one transmitter (10d), a buffer circuit (50) for assembling into a data packet in parallel a number of sample conversion words from said transmitter, a marker circuit for adding a marker word (48) to said data packet for framing said data packet, and a serializer (54) circuit for serializing said data packet either before or after said marker word is added, with an embedded clock for transmission.