Embedded-Clock Transceiver Using Dummy Bits for Data Type Detection
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Solution Overview
Problem
Transceivers that embed clock signals in data face challenges in accurately identifying the type of data components, particularly when payload information is present or absent, leading to inefficiencies in data transmission and reception.
Innovation Solution
The method involves converting data components into serial data by adding dummy bits at predetermined intervals, where the logical state of the dummy bits indicates the type of data components, allowing the receiver to identify the type by comparing the logical states of adjacent bits, and using phase or delay locked loops to generate and synchronize clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signal is embedded in data transmission, then transmission efficiency is improved, but data type identification accuracy deteriorates
Solution Approach 1:
The patent introduces dummy bits as intermediary elements that carry metadata information about data types. These dummy bits act as mediators between the data components and the receiver, enabling the receiver to identify data types without requiring separate signaling channels, thus maintaining transmission efficiency while improving identification accuracy.
Solution Approach 2:
The patent segments the data stream by inserting dummy bits at predetermined intervals between actual data components. This segmentation allows the receiver to distinguish between data components and dummy bits, and to extract data type information from the dummy bits without affecting the integrity of the actual data transmission.
2Measurement precision
If dummy bits are added to indicate data types, then data type identification is improved, but transmission overhead increases
Solution Approach 1:
The patent applies local quality by making dummy bits have distinct logical states (e.g., all zeros or all ones) that differ from normal data bits. This local differentiation allows the receiver to easily identify and process dummy bits without confusing them with actual data, improving identification accuracy while keeping the overhead minimal and predictable.
3Measurement precision
If separate clock and data lines are used, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock signal function into the data transmission channel by using dummy bits to carry timing and synchronization information. This consolidation eliminates the need for separate clock lines, reducing interface complexity while maintaining synchronization accuracy through the embedded timing information in the dummy bits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate identification of data types and efficient data transmission and reception, improving synchronization and reducing errors in transceivers, especially in display devices where data components include payload information.
Implementation Method 1
a phase locked loop for generating the clock signal based on the serial data
Implementation Method 2
a delay locked loop for generating the clock signal based on the serial data
Data Source
AI summary
A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.