Embedded Clock Receiver Using Four-Wire Three-Level Signaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed digital data communications in processors face challenges with parallel communication techniques due to high power consumption and power supply noise, and SerDes technologies are complex, consuming significant die area and potentially adding failure points, especially when used for on-die communications.
Innovation Solution
A digital receiver system using four wires with three signaling levels (-1, 0, +1) embeds the clock signal within the data stream, allowing for simultaneous transmission of two data bits and a clock signal, minimizing external interaction and eliminating the need for separate clock lines, thereby reducing power consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel data communication technique is used, then data transfer rate is improved, but power consumption increases and power supply noise increases
Solution Approach 1:
The patent combines the clock signal transmission with data signal transmission by using the same physical medium (power delivery network) for both purposes. The receiver extracts timing information from the combined signal, eliminating the need for separate clock lines and reducing overall power consumption while maintaining high data transfer rates.
2Productivity
If SerDes technology is used, then data communication capability is improved, but device complexity increases and die area increases
Solution Approach 1:
The patent makes the power delivery network serve multiple functions: it provides both power delivery and clock signal transmission simultaneously. This multi-functionality eliminates the need for dedicated SerDes components and separate clock distribution infrastructure, significantly reducing device complexity while maintaining communication capability.
3Measurement precision
If separate clock line is used, then timing synchronization is improved, but device complexity increases and power consumption increases
Solution Approach 1:
The patent merges clock signal transmission with data signal transmission by using the same physical medium (power delivery network) for both purposes. The receiver extracts timing information from the combined signal, eliminating the need for separate clock lines and reducing overall power consumption while maintaining high data transfer rates.
Solution Approach 2:
The patent makes the power delivery network serve multiple functions: it provides both power delivery and clock signal transmission simultaneously. This multi-functionality eliminates the need for dedicated SerDes components and separate clock distribution infrastructure, significantly reducing device complexity while maintaining communication capability.
Data Source
AI summary
A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.