Data-Embedded Clock Transceiver for Compact Memory Interfaces
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Solution Overview
Problem
In massively parallel short-reach memory interfaces, the large number of inputs/outputs (I/O) increases the area requirements of transmitters and receivers, and there is a need to accurately distribute a clock to a large number of transmitters and receivers, which is inefficient due to the inclusion of clocking circuits.
Innovation Solution
A data transmitter generates a data embedded clock signal, eliminating the need for separate clock and data recovery (CDR) and clock and data alignment (CDA) circuits in the receiver, by transmitting both data and clock signals together.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate clock and data recovery (CDR) circuits and clock and data alignment (CDA) circuits are included in the receiver, then accurate clock distribution and data recovery are achieved, but the area of the receiver increases
Solution Approach 1:
The patent merges the clock signal and data signal into a single transmitted signal by embedding clock information within the data stream. The receiver recovers both clock and data from this combined signal, eliminating the need for separate CDR and CDA circuits and thereby reducing receiver area while maintaining accurate recovery
Solution Approach 2:
The transmitted signal serves multiple functions simultaneously: it carries both data information and clock synchronization information. This multi-functionality allows the receiver to extract both data and clock timing from a single signal source, eliminating the need for separate dedicated circuits
2Productivity
If a large number of inputs/outputs (I/O) are used in massively parallel short-reach memory interfaces, then data transmission capacity is increased, but the area of transmitters and receivers increases
Solution Approach 1:
By merging clock and data into a single transmitted signal, the patent reduces the number of separate signal paths and associated circuitry needed in transmitters and receivers. This consolidation maintains high data transmission capacity through parallel I/O while reducing the overall transceiver area
Data Source
AI summary
A data transmitter includes a transmitting circuit configured to transmit data, the data including alternating odd-numbered data and even-numbered data. The transmitting circuit includes a first flip flop configured to receive the odd-numbered data and generate retimed odd-numbered data, and a second flip flop configured to receive the even-numbered data and generate retimed even-numbered data. The data transmitter includes a clock transmitting circuit configured to supply a clock signal to the transmitting circuit, the clock transmitting circuit including a clock driver configured to transmit the clock signal to a receiver that receives the data.