Embedded Clock Signals in Network Packets for Distributed Timing
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Solution Overview
Problem
In distributed computing environments, synchronizing time across multiple computing devices is challenging due to independent notions of time, leading to difficulties in resolving conflicting requests and implementing time-based policies, with existing techniques being inaccurate or too complex for wide-scale deployment.
Innovation Solution
A clock distribution network transmits clock signals within network packets, embedding additional metadata for authentication, validation, and timestamping, using programmable ICs like FPGAs to ensure accurate synchronization across virtual machines and server computers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Network Time Protocol (NTP) is used to synchronize time between networked computers, then time synchronization is achieved, but accuracy is insufficient and complexity increases for wide-scale deployment
Solution Approach 1:
The patent extracts the clock signal transmission from standard network protocols and implements it through a dedicated clock distribution network. This separation allows for specialized hardware (programmable ICs, FPGAs) to handle time synchronization independently, achieving higher accuracy without burdening the main system complexity.
Solution Approach 2:
The patent introduces an intermediary clock distribution network that acts as a dedicated mediator between time sources and computing devices. This intermediary layer provides precise clock signals through specialized infrastructure, improving accuracy while keeping the complexity isolated to the intermediary layer rather than propagating through the entire distributed system.
2Measurement precision
If existing time synchronization techniques are implemented in distributed computing platforms, then time information is provided, but accuracy is insufficient and deployment complexity increases
Solution Approach 1:
The patent segments the time synchronization function into a dedicated clock distribution network separate from the general data network. This segmentation allows each component to be optimized independently - the clock network for accuracy and the data network for versatility - making deployment easier while achieving higher precision.
Solution Approach 2:
The patent implements periodic clock signal distribution through the clock distribution network, providing regular time synchronization pulses to computing devices. This periodic action ensures consistent accuracy while simplifying deployment through standardized, recurring synchronization events rather than complex continuous negotiation protocols.
3Reliability
If clock signals are transmitted through standard network protocols, then time information is conveyed, but additional metadata for authentication and validation cannot be effectively included
Solution Approach 1:
The patent merges the clock signal transmission with additional metadata (authentication, validation, timestamps) into a unified packet structure within the dedicated clock distribution network. This combination ensures that all necessary information travels together, preventing information loss while maintaining reliability through integrated validation mechanisms.
Solution Approach 2:
The patent creates a universal packet structure that carries both clock signals and multiple types of metadata simultaneously. This multi-functional approach allows a single transmission to provide timing, authentication, validation, and other information, eliminating the need for separate protocols and reducing information loss.
Data Source
AI summary
A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The network packets can include a preamble used to create phase alignment between a timing pulse and a bit position of a Start of Frame Delimiter (SFD) within the packet. The clock signal associated with the packet occurs when the SFD is detected. In one example, the SFD is detected when two consecutive bits of equal value are received and the timing of the clock signal is such that the clock signal occurs when the second consecutive bit is received. By including a clock signal within a packet, additional information can be transmitted with the clock signal. For example, authentication and validation information can be included, a time stamp, a message type, a frame check sequence, a clock status, a number of hops from the root, etc.