Embedded Clock Recovery for Data Rate Synchronization

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Solution Overview

Problem

Existing methods for clock synchronization between a source and sink device in data communications, particularly for isochronous data streams, face challenges such as incompatibilities due to differing link data rates, variable delays, and increased complexity and cost in intermediate devices, especially when the sink device is not directly coupled to the source.

Innovation Solution

The method involves forming a logical channel to transmit a source data stream with embedded rate parameters, allowing the sink device to detect and recover the source data rate by determining the logical channel and source data stream rates, eliminating the need for parsing embedded data and reducing complexity in intermediate devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional methods transmit rate parameters from source to sink, then clock synchronization is achieved, but incompatibilities occur when link data rates differ between source and sink

Engineering Contradiction:
Improveclock synchronizationVSAvoidcompatibility with different link data rates
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces an intermediate device (such as a switch or router) that regenerates rate parameters based on incoming and outgoing link rates. This intermediary translates the rate relationship information between different link layers, allowing the sink device to correctly interpret the source data rate even when link rates differ. The intermediate device acts as a mediator that adapts the parameter format to match the local link characteristics.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a buffer is used at the sink device to determine clock rate, then clock recovery is enabled, but variable delays and expensive buffer requirements are introduced

Engineering Contradiction:
Improveclock recoveryVSAvoidbuffer requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the rate parameter information from the data stream and transmits it separately through a dedicated control channel or metadata field. By separating the timing information from the data payload, the sink device can determine clock rate without requiring large buffers to absorb timing variations. The extracted rate parameters provide direct timing guidance, eliminating the need for complex buffer-based clock recovery mechanisms.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If intermediate devices regenerate rate parameters, then clock synchronization is maintained across multiple devices, but device complexity and cost increase

Engineering Contradiction:
Improveclock synchronization across multiple devicesVSAvoidintermediate device complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the rate parameter transmission into distinct components: source data rate information, link rate information, and derived relationship parameters. Each intermediate device only needs to process and regenerate specific segments of this information based on its local link characteristics. This segmentation allows intermediate devices to perform simple parameter transformations rather than complex full-scale clock recovery and regeneration, reducing their complexity while maintaining synchronization.

Inventive Principle:
Principle #1Segmentation

4Adaptability or versatility

If the sink device is not directly coupled to the source device, then system flexibility is improved, but accurate source data rate recovery becomes more difficult

Engineering Contradiction:
Improvesystem flexibilityVSAvoidsource data rate recovery accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent implements preliminary action by having the source device embed rate parameters and having intermediate devices pre-calculate and regenerate these parameters before data arrives at the sink. The rate relationship information is prepared in advance and transmitted through the data stream or control channels, so when the sink device receives the data, the timing information is already available and accurate. This preliminary preparation ensures that even with indirect coupling through multiple intermediate devices, the sink can accurately recover the source data rate without requiring direct connection to the source.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3664323B1Embedded clock recovery
Publication Date: 2021.07.07 ATI TECHNOLOGIES ULC
  • EP3664323B1 patent drawingFigure 1
  • EP3664323B1 patent drawingFigure 2
  • EP3664323B1 patent drawingFigure 3

AI summary

Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. A method for a sink device to recover a source data rate includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters. Corresponding systems and computer program products are also described.