Embedded Clock RZ Signaling for High-Speed On-Die Communication
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Solution Overview
Problem
High-speed data communication in processors faces challenges with parallel data lines due to power supply noise and complexity, and serializer/deserializer (SerDes) technology is inefficient in terms of design effort, die area, and power consumption, especially for on-die communications.
Innovation Solution
The implementation of a return-to-zero (RZ) signaling scheme with multiple voltage levels to embed the clock signal within the data stream, eliminating the need for clock recovery circuits and reducing latency, while using a modified two-bit digital-to-analog converter to generate and decode signals with additional levels for efficient data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel data lines with buffers are used for high-speed communication, then data communication rate is improved, but power supply noise increases due to large dynamic currents
Solution Approach 1:
The patent combines clock signal and data signal into a single communication channel using RZ encoding. The clock transitions are embedded within the data signal itself, eliminating the need for separate clock lines and reducing the number of buffers required, thereby reducing power supply noise while maintaining high data communication rates
Solution Approach 2:
The RZ-encoded signal serves multiple functions simultaneously: it carries data information and embedded clock information for synchronization. This multi-functionality reduces the need for separate dedicated clock circuits and buffers, lowering overall power consumption and reducing power supply noise
2Speed
If SerDes technology is used for data communication, then data communication rate is improved, but device complexity and die area increase
Solution Approach 1:
The patent extracts the clock signal from the data stream using RZ encoding, where clock transitions are embedded within the data signal itself. This eliminates the need for complex external clock recovery circuits typically required in SerDes systems, reducing device complexity while maintaining high-speed communication capabilities
Solution Approach 2:
The data signal itself provides the clock information through its RZ encoding scheme. The signal's own transitions serve as the clock reference for sampling, eliminating the need for separate clock recovery mechanisms and reducing overall system complexity
3Speed
If SerDes technology is used for data communication, then data communication rate is improved, but power consumption increases
Solution Approach 1:
The patent merges clock and data transmission into a single channel using RZ encoding. This consolidation reduces the number of separate circuits and buffers required, thereby reducing overall power consumption while achieving high-speed data communication
4Reliability
If separate clock signal is used for data communication, then data synchronization is improved, but device complexity and die area increase
Solution Approach 1:
The patent combines clock and data signals into a single RZ-encoded communication channel. The embedded clock transitions within the data signal provide synchronization without requiring separate clock lines or additional die area for clock distribution circuits
Data Source
AI summary
Transmitter circuitry transmits: a first voltage as the return-to-zero signal that is higher than a first positive threshold, the first voltage being decodable to a first order of data bits; a second voltage as a return-to-zero signal that is between a second positive threshold and the first positive threshold, the second voltage being decodable to a second order of the data bits, and the second positive threshold being lower than the first positive threshold; a third voltage as the return-to-zero signal that is between a first negative threshold and a second negative threshold, the third voltage being decodable to a third order of the data bits, and the second negative threshold being higher than the first negative threshold; and a fourth voltage as the return-to-zero signal that is lower than the first negative threshold, the fourth voltage being decodable to a fourth order of the data bits. Clock circuitry transitions a clock signal for the return-to-zero signal crossing the second positive threshold, and for the return-to-zero signal crossing the second negative threshold.