Embedded Clock RZ Signaling for Low-Complexity On-Die Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed data communication in processors faces challenges with parallel data lines due to power supply noise and complexity, and serializer/deserializer (SerDes) technology is inefficient in terms of design effort, die area, and power consumption, especially for on-die communications.
Innovation Solution
The method employs return-to-zero (RZ) signaling with multiple voltage levels to embed the clock signal within the data stream, allowing for efficient transmission of data bits and clock signals using a reduced number of conductors and eliminating the need for clock recovery circuits, thereby reducing power consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel data lines with buffers are used for high-speed communication, then data communication rate is improved, but power supply noise increases due to large dynamic currents
Solution Approach 1:
The patent combines the clock signal and data signals into a single communication channel using RZ encoding. The clock transitions are embedded within the data stream itself, eliminating the need for separate clock lines and reducing the number of buffers required, thereby reducing power supply noise while maintaining high data communication rates
Solution Approach 2:
The RZ-encoded signal serves multiple functions simultaneously: it carries data information and embedded clock information for synchronization. This multi-functionality eliminates the need for separate clock circuits and buffers, reducing power consumption and noise while achieving high-speed communication
2Speed
If SerDes technology is used for data communication, then communication rate is improved, but design complexity and die area increase significantly
Solution Approach 1:
The patent extracts the clock signal from the data stream using RZ encoding, where clock transitions are embedded within the data itself. This eliminates the need for complex SerDes clock recovery circuits, significantly reducing design complexity while maintaining high communication rates
Solution Approach 2:
The patent changes the signaling scheme from traditional NRZ to RZ encoding, which embeds clock information in the signal transitions. This parameter change simplifies the receiver design by eliminating the need for separate clock recovery circuits, reducing design complexity while achieving high-speed communication
3Speed
If SerDes technology is used for data communication, then communication rate is improved, but die area consumption increases
Solution Approach 1:
The patent merges the clock signal and data signal into a single RZ-encoded channel. This consolidation eliminates the need for separate clock recovery circuits and associated components in the SerDes, significantly reducing die area while maintaining high communication rates
Solution Approach 2:
The patent extracts clock information from the data stream itself through RZ encoding, eliminating the need for complex SerDes infrastructure. This extraction approach reduces die area by removing unnecessary clock recovery circuits and synchronization components
4Productivity
If parallel data lines are used for communication, then data communication capability is improved, but the technique is incompatible with on-die communications due to complexity
Solution Approach 1:
The RZ-encoded signal provides universal functionality by carrying both data and clock information in a single channel. This simplifies the communication interface, making it suitable for on-die communications where space and power are constrained, while maintaining high data communication capability
Data Source
AI summary
A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.