Semaphore-Governed Neural Network Circuit for Embedded CNN Throughput
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Solution Overview
Problem
Convolutional neural networks are difficult to implement in embedded devices like IoT devices due to large-scale dedicated circuits and limited hardware resources, making high-performance operation challenging.
Innovation Solution
A neural network circuit design with a first and second memory, a convolution operation circuit, a quantization operation circuit, and semaphores for controlling data access, allowing for efficient data transfer and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large-scale dedicated circuits are used for convolutional neural networks, then operational performance is improved, but device complexity increases and embeddability in IoT devices deteriorates
Solution Approach 1:
The patent segments the neural network processing into distinct functional blocks: convolution operation circuit, quantization operation circuit, and pooling operation circuit. Each block handles specific operations independently, allowing the system to achieve high operational performance through coordinated specialized units rather than a monolithic large-scale circuit, thus improving embeddability in IoT devices.
Solution Approach 2:
The patent designs memory units and control circuits that serve multiple functions. For example, the first memory stores both input data and intermediate results, while the control circuit manages data flow between different operation circuits and memory units, enabling a compact design that achieves high performance without increasing overall device complexity.
2Productivity
If more hardware resources are allocated to neural network operations, then computational capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic data transfer between memory and operation circuits controlled by semaphores. The control circuit enables data transfer only when synchronization conditions are met, avoiding continuous memory access and reducing unnecessary power consumption while maintaining high computational capability through efficient periodic operations.
Solution Approach 2:
The patent introduces semaphore-based control as an intermediary mechanism between memory units and operation circuits. This mediator coordinates data flow, ensuring that memory access occurs only when needed, thereby reducing overall system power consumption while preserving computational capability through optimized resource utilization.
3Speed
If parallel processing is implemented to accelerate neural network operations, then processing speed is improved, but control complexity increases
Solution Approach 1:
The patent implements feedback control through semaphores that monitor the state of memory units and operation circuits. The control circuit continuously checks semaphore values to determine when data transfer is appropriate, enabling coordinated parallel processing between convolution, quantization, and pooling circuits while maintaining manageable control complexity through systematic feedback mechanisms.
Data Source
AI summary
A method for controlling a neural network circuit that is provided with a first memory, a convolution operation circuit that performs a convolution operation, a second memory, a quantization operation circuit, a second write semaphore, a second read semaphore, a third write semaphore, and a third read semaphore, wherein the method for controlling the neural network circuit involves making the convolution operation circuit implement a convolution operation based on the third read semaphore and the second write semaphore.