Embedded Codec Randomized Bit Refinement

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Solution Overview

Problem

Conventional image and video compression techniques using on-chip codecs face inefficiencies due to coding artifacts and sub-optimal memory usage, particularly in embedded systems, where un-coded bits are refined using a fixed refinement order, leading to compression inefficiency and area throughput issues.

Innovation Solution

An embedded codec circuitry and method for randomized refinement of un-coded bits, where the refinement start position is determined based on a random number and step size, ensuring a uniform distribution of refinement bits across bit-planes, reducing coding artifacts and improving compression efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed refinement order is used for un-coded bits, then the encoding process is simple and deterministic, but coding artifacts appear and compression efficiency deteriorates

Engineering Contradiction:
Improvecompression efficiencyVSAvoidrefinement process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by transforming the static fixed refinement order into a dynamic randomized refinement order. The refinement start position is determined by a random number, and the refinement step size varies, creating a dynamic refinement sequence that adapts to different encoding scenarios. This dynamic approach prevents systematic artifacts while maintaining encoding efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of refinement order from fixed to randomized by introducing random numbers and varying step sizes. The refinement start position and step size are modified parameters that control the refinement process, allowing the system to achieve better compression efficiency by distributing refinement bits more uniformly across the bit-plane.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If refinement bits are allocated in a fixed order, then memory access pattern is predictable, but uniform distribution of refinement bits is not achieved and coding artifacts occur

Engineering Contradiction:
Improveuniform distribution of refinement bitsVSAvoidrefinement bit distribution control
Core Design Contradiction:
Manufacturing precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent uses dynamic refinement step sizes and random start positions to achieve uniform distribution of refinement bits. The step size is adjusted based on the random number generated, creating a dynamic allocation pattern that ensures better coverage and uniformity across the bit-plane without requiring complex control mechanisms.

Inventive Principle:
Principle #15Dynamics

3Productivity

If conventional fixed refinement is used, then area efficiency is reduced, but the implementation is simpler

Engineering Contradiction:
Improvearea throughputVSAvoidrefinement circuitry complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic refinement with random start positions and variable step sizes using relatively simple circuitry. The randomness is introduced through minimal additional components (random number generator and step size controller), achieving improved area throughput without proportionally increasing device complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10778990B2Embedded codec circuitry for randomized refinement of uncoded-bits
Publication Date: 2020.09.15 SONY GROUP CORP
  • US10778990B2 patent drawing
  • US10778990B2 patent drawing
  • US10778990B2 patent drawing

AI summary

An embedded codec (EBC) circuitry includes encoder circuitry to determine a refinement start position in a bit-plane of an encoded data block based on a random number. The refinement start position is a position in the bit-plane based on a value of the random number. The encoder circuitry determines a refinement order in the bit-plane for refining un-coded bits present in the bit-plane, based on the determined refinement start position and a refinement step size. The refinement order is a sequence of positions of the un-coded bits in the bit-plane that will be refined in that sequence. The encoder circuitry refines the un-coded bits by allocating a refinement bit at the refinement start position in the bit-plane and then followed by the allocation of subsequent refinement bits in the determined refinement order.