Embedded Cold Plate Packaging to Cut Chip Thermal Resistance
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Solution Overview
Problem
Existing cooling systems for microelectronic devices face inefficiencies due to high thermal resistance at interfacial boundaries, which hinder effective heat transfer from chips to heat dissipation devices, leading to reduced cooling efficiency and performance degradation.
Innovation Solution
Integrated cooling assemblies are embedded within device packages, directly bonding the semiconductor device to a cold plate without intervening thermal interface materials, using direct dielectric or hybrid bonding, and forming a coolant channel sealed by an adhesive layer to enhance heat transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal interface materials are used to couple the chip to heat dissipation devices, then thermal contact is maintained, but thermal resistance at interfacial boundaries increases, reducing cooling efficiency
Solution Approach 1:
The patent removes thermal interface materials from the thermal path between the chip and heat dissipation devices. By directly bonding the cold plate to the semiconductor device, the intermediate thermal resistance layer (TIM) is extracted from the system, eliminating its harmful thermal blocking effect while maintaining necessary thermal contact through direct bonding interfaces
Solution Approach 2:
The patent merges the chip and heat dissipation device into a single integrated thermal assembly by directly bonding the cold plate to the semiconductor device. This merging eliminates the separate thermal interface material layer and creates a unified thermal path, reducing overall thermal resistance while maintaining reliable thermal coupling
2Ease of manufacture
If conventional cooling systems are used with thermal interface materials, then device assembly is simplified, but cooling efficiency decreases due to thermal resistance
Solution Approach 1:
The patent replaces the mechanical compression and bonding system used with thermal interface materials with a direct dielectric or hybrid bonding system. This substitution eliminates the need for separate TIM application, positioning, and compression steps, while achieving superior thermal coupling through direct material-to-material bonding at the interface
3Loss of energy
If direct bonding is used to attach cold plate to semiconductor device, then thermal resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary preparation of bonding surfaces and bonding parameter optimization before the actual direct bonding process. By pre-characterizing the semiconductor device backside and cold plate bonding surfaces, and pre-determining optimal bonding conditions (temperature, pressure, time), the complex direct bonding process becomes more controllable and manufacturable
Solution Approach 2:
The patent utilizes parameter changes in the bonding process (temperature, pressure, time) to achieve direct bonding without excessive complexity. By controlling these parameters within specific ranges, the bonding process becomes repeatable and manufacturable, transforming a potentially complex process into a controlled industrial operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces thermal resistance, enhancing cooling efficiency by 50× or more, while maintaining device integrity and preventing coolant leakage, thus improving performance and reliability.
Implementation Method 1
An adhesive layer may be disposed between the package cover and the second side of the cold plate... The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel
Implementation Method 2
a cold plate having a first side attached to the semiconductor device... one or more surfaces of the second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween
Data Source
AI summary
In some implementations, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.