Embedded Comparator Offset Cancellation for Pipeline Flash ADCs
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Solution Overview
Problem
Existing systems fail to efficiently and controllably calibrate comparator offsets in pipeline analog-to-digital converters, particularly in flash ADCs, without affecting converter speed or adding significant power, as existing methods either distort gain or introduce parasitic capacitance.
Innovation Solution
A system and method that calibrate comparator offsets on a per-comparator basis by injecting a calibration current or voltage at designated points using a low-power DAC, controlled by a digital codeword generated based on the comparator's output, without affecting the speed or power consumption of the pipeline ADC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-gain preamplifier is used to cancel comparator offset, then the offset cancellation is achieved, but the circuit area increases and the overall gain is distorted
Solution Approach 1:
The patent extracts the offset cancellation function from a separate preamplifier circuit and integrates it directly into the comparator latch nodes. By taking out the need for external offset correction circuitry and embedding the cancellation capability within the comparator itself, the solution achieves offset cancellation without adding significant circuit area or distorting overall gain.
Solution Approach 2:
The patent merges the offset storage and cancellation functions with the existing comparator latch nodes. By combining multiple functions (comparing, latching, and offset cancellation) into a single integrated structure, the solution eliminates the need for separate preamplifier circuits while maintaining effective offset correction.
2Measurement precision
If capacitors are used within comparator latch nodes to store and cancel offset, then offset calibration is achieved, but parasitic capacitance is introduced that slows down the converter
Solution Approach 1:
The patent changes the physical parameters of the latch nodes by adjusting transistor widths and bias conditions to accommodate offset storage and cancellation functionality. By modifying electrical parameters (transistor dimensions, bias currents) rather than adding physical capacitive elements, the solution achieves offset calibration without introducing parasitic capacitance that would slow down the converter.
3Measurement precision
If comparator offset is minimized to distribute allocation for sampling bandwidth mismatch, then measurement accuracy improves, but the complexity of offset removal increases
Solution Approach 1:
The patent implements self-service by enabling each comparator to automatically calibrate its own offset through integrated latch node manipulation. The comparator system performs its own offset correction without requiring external calibration equipment or complex control circuits, thereby improving measurement precision while keeping the offset removal process simple and automated.
Data Source
AI summary
A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.